A Discrete Fourier Analyzer Based on Analog VLSI Technology

Shoji KAWAHITO; Kazuyuki TAKEDA; Takanori NISHIMURA; Yoshiaki TADOKORO

A Discrete Fourier Analyzer Based on Analog VLSI Technology

Shoji KAWAHITO, Kazuyuki TAKEDA, Takanori NISHIMURA, Yoshiaki TADOKORO

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This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.7 pp.1049-1056

Publication Date: 1994/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)

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Shoji KAWAHITO, Kazuyuki TAKEDA, Takanori NISHIMURA, Yoshiaki TADOKORO, "A Discrete Fourier Analyzer Based on Analog VLSI Technology" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 7, pp. 1049-1056, July 1994, doi: .
Abstract: This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_7_1049/_p

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@ARTICLE{e77-c_7_1049,
author={Shoji KAWAHITO, Kazuyuki TAKEDA, Takanori NISHIMURA, Yoshiaki TADOKORO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Discrete Fourier Analyzer Based on Analog VLSI Technology},
year={1994},
volume={E77-C},
number={7},
pages={1049-1056},
abstract={This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Discrete Fourier Analyzer Based on Analog VLSI Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1049
EP - 1056
AU - Shoji KAWAHITO
AU - Kazuyuki TAKEDA
AU - Takanori NISHIMURA
AU - Yoshiaki TADOKORO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1994
AB - This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.
ER -