In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (αVth) extractor is also described, in which α varies continuously. Both incremental and decremental αVth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

The design of the analog part of a mixed analog-digital IC for a commercial wireless burglar alarm system is presented as an example of a very low-power VLSI design for battery-operated systems. The main constraint is battery life, which must be at least five years (with standard camera-battery). An operational amplifier, a power supply monitor and an oscillator are the core of the design. The operational amplifier absorbs 1.5 µA while the entire analog part absorbs 4 µA. Measures on each single part show compliance with specification. Test on working environment show its full functionality. Even though the example is application specific, the design solutions and each single element can also be utilized in many other battery-operated low-frequency devices (e.g. environmental parameter monitoring).

In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.

In this paper we present a case study of a hierarchical statistical analysis. The method which we use here bridges the statistical information between process-level and system-level, and enables us to know the effect of the process variation on the system performance. We use two modeling techniques--intermediate model and response surface model--in order to link the statistical information between adjacent design levels. We show an experiment of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL) circuit, and indicate that the hierarchical statistical analysis is practical with respect to both accuracy and simulation cost. Following three applications are also presented in order to show advantage of this linking method; these are Monte Carlo analysis, worst-case analysis, and sensitive analysis. The results of the Monte Carlo and the worst-case analysis indicate that this method is realistic statistical one. The result of the sensitive analysis enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.