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[Author] Yutaka FUKUI(33hit)

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  • Electronically Tunable Current-Mode Biquad Using OTAs and Grounded Capacitors

    Takao TSUKUTANI  Masami HIGASHIMURA  Yasuaki SUMI  Yutaka FUKUI  

     
    LETTER-Analog Signal Processing

      Vol:
    E84-A No:10
      Page(s):
    2595-2599

    This paper introduces current-mode biquad using multiple current output operational transconductance amplifiers (OTAs) and grounded capacitors. The circuit configuration is obtained from a second-order integrator loop structure with loss-less and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. It is also made clear that the proposed circuit has very low sensitivities with respect to the circuit active and passive elements. An example is given together with simulated results by PSpice.

  • Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using a Target Frequency Detector

    Shigeki OBOTE  Yasuaki SUMI  Naoki KITAI  Kouichi SYOUBU  Yutaka FUKUI  Yoshio ITOH  

     
    PAPER

      Vol:
    E82-A No:3
      Page(s):
    436-441

    In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.

  • PLL Frequency Synthesizer with Multi-Phase Detector

    Yasuaki SUMI  Kouichi SYOUBU  Shigeki OBOTE  Yutaka FUKUI  Yoshio ITOH  

     
    PAPER

      Vol:
    E82-A No:3
      Page(s):
    431-435

    The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

  • A Newton Based Adaptive Algorithm for IIR ADF Using Allpass and FIR Filter

    James OKELLO  Yoshio ITOH  Yutaka FUKUI  Masaki KOBAYASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E82-A No:7
      Page(s):
    1305-1313

    Newton based adaptive algorithms are among the algorithms which are known to exhibit a higher convergence speed in comparison to the least mean square (LMS) algorithms. In this paper we propose a simplified Newton based adaptive algorithm for an adaptive infinite impulse response (IIR) filter implemented using cascades of second order allpass filters and a finite impulse response (FIR) filter. The proposed Newton based algorithm avoids the complexity that may arise in the direct differentiation of the mean square error. The analysis and simulation results presented for the algorithm, show that the property of convergence of the poles of the IIR ADF to those of the unknown system will be maintained for both white and colored input signal. Computer simulation results confirm an increase in convergence speed in comparison to the LMS algorithm.

  • Parallel Composition Based Adaptive Notch Filter: Performance and Analysis

    Arata KAWAMURA  Yoshio ITOH  James OKELLO  Masaki KOBAYASHI  Yutaka FUKUI  

     
    PAPER-Digital Signal Processing

      Vol:
    E87-A No:7
      Page(s):
    1747-1755

    In this paper we propose a parallel composition based adaptive notch filter for eliminating sinusoidal signals whose frequencies are unknown. The proposed filter which is implemented using second order all-pass filter and a band-pass filter can achieve high convergence speed by using the output of an additional band-pass filter to update the coefficients of the notch filter. The high convergence speed of the proposed notch filter is obtained by reducing an effect that an updating term of coefficient for adaptation of a notch filter significantly increases when the notch frequency approaches the sinusoidal frequency. In this paper, we analyze such effect obtained by the additional band-pass filter. We also present an analysis of a convergence performance of cascaded system of the proposed notch filter for eliminating multiple sinusoids. Simulation results have shown the effectiveness of the proposed adaptive notch filter.

  • A Realization of Multiple Circuit Transfer Functions Using OTA-C Integrator Loop Structure

    Takao TSUKUTANI  Masami HIGASHIMURA  Yasutomo KINUGASA  Yasuaki SUMI  Yutaka FUKUI  

     
    LETTER-Analog Signal Processing

      Vol:
    E86-A No:2
      Page(s):
    509-512

    This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

  • A New Linear Prediction Filter Based Adaptive Algorithm For IIR ADF Using Allpass and Minimum Phase System

    James OKELLO  Yoshio ITOH  Yutaka FUKUI  Masaki KOBAYASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E81-A No:1
      Page(s):
    123-130

    An adaptive infinite impulse response (IIR) filter implemented using an allpass and a minimum phase system has an advantage of its poles converging to the poles of the unknown system when the input is a white signal. However, when the input signal is colored, convergence speed deteriorates considerably, even to the point of lack of convergence for certain colored signals. Furthermore with a colored input signal, there is no guarantee that the poles of the adaptive digital filter (ADF) will converge to the poles of the unknown system. In this paper we propose a method which uses a linear predictor filter to whiten the input signal so as to improve the convergence characteristic. Computer simulation results confirm the increase in convergence speed and the convergence of the poles of the ADF to the poles of the unknown system even when the input is a colored signal.

  • PLL Frequency Synthesizer for Low Power Consumption

    Yasuaki SUMI  Kouichi SYOUBU  Kazutoshi TSUDA  Shigeki OBOTE  Yutaka FUKUI  

     
    PAPER

      Vol:
    E80-A No:3
      Page(s):
    461-465

    In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

  • An Adaptive Algorithm for Cascaded Notch Filter with Reduced Bias

    James OKELLO  Shin'ichi ARITA  Yoshio ITOH  Yutaka FUKUI  Masaki KOBAYASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E84-A No:2
      Page(s):
    589-596

    In this paper we propose a new simplified algorithm for cascaded second order adaptive notch filters implemented using an allpass filter, for elimination of multiple sinusoids. Each of the stages of the notch filter is implemented using direct form second order allpass filter. We also present an analysis which compares the proposed algorithm with the conventional simplified algorithm, and which indicates that the proposed algorithm has a reduced bias in the estimation of the multiple input sinusoids. Simulation results that have been provided confirm this analysis.

  • Region Extraction Using Color Feature and Active Net Model in Color Image

    Noboru YABUKI  Yoshitaka MATSUDA  Hiroyuki KIMURA  Yutaka FUKUI  Shigehiko MIKI  

     
    PAPER

      Vol:
    E82-A No:3
      Page(s):
    466-472

    In this paper, we propose a method to detect a road sign from a road scene image in the daytime. In order to utilize color feature of sign efficiently, color distribution of sign is examined, and then color similarity map is constructed. Additionally, color similarity shown on the map is incorporated into image energy of an active net model. A road sign is extracted as if it is wrapped up in an active net. Some experimental results obtained by applying an active net to images are presented.

  • A Simple Algorithm for Adaptive Allpass-FIR Digital Filter Using Lattice Allpass Filter with Minimum Multipliers

    James OKELLO  Yoshio ITOH  Yutaka FUKUI  Masaki KOBAYASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E82-A No:1
      Page(s):
    138-144

    Adaptive infinite impulse response (IIR) digital filter implemented using a cascade of second order direct form allpass filters and a finite impulse response (FIR) filter, has the property of its poles converging to those of the unknown system. In this paper we implement the adaptive allpass-FIR digital filter using a lattice allpass filter with minimum number of multipliers. We then derive a simple adaptive algorithm, which does not increase the overall number of multipliers of the proposed adaptive digital filter (ADF) in comparison to the ADF that uses the direct form allpass filter. The proposed structure and algorithm exhibit a kind of orthogonality, which ensures convergence of the poles of the ADF to those of the unknown system. Simulation results confirm this convergence.

  • Improvement of Active Net Model for Region Detection in an Image

    Noboru YABUKI  Yoshitaka MATSUDA  Makoto OTA  Yasuaki SUMI  Yutaka FUKUI  Shigehiko MIKI  

     
    PAPER

      Vol:
    E84-A No:3
      Page(s):
    720-726

    Processes in image recognition include target detection and shape extraction. Active Net has been proposed as one of the methods for such processing. It treats the target detection in an image as an energy optimization problem. In this paper, a problem of the conventional Active Net is presented and the new Active Net is proposed. The new net is improved the ability for detecting a target. Finally, the validity of the proposed net is confirmed by experimental results.

  • The Automatic Counting of Chlorella Using Image Processing and Neural Network

    Yasuaki SUMI  Makoto OTA  Noboru YABUKI  Shigeki OBOTE  Yoshitaka MATSUDA  Yutaka FUKUI  

     
    LETTER

      Vol:
    E84-A No:3
      Page(s):
    794-796

    In the culture of marine chlorellas, it is necessary to count the number in order to understand the condition of increase. For that propose, counting by the naked eye using the microscope has been used. However, this method requires a lot of time and work. We have developed the automatic chlorella counter using image processing and neural network. Its effectiveness is confirmed through the experiment.

  • PLL Frequency Synthesizer with Binary Phase Comparison

    Shigeki OBOTE  Yasuaki SUMI  Naoki KITAI  Yutaka FUKUI  Yoshio ITOH  

     
    PAPER

      Vol:
    E83-A No:3
      Page(s):
    427-434

    In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.

  • FOREWORD

    Yutaka FUKUI  

     
    FOREWORD

      Vol:
    E80-A No:8
      Page(s):
    1351-1351
  • Reduction of Computational Complexity in the IA Algorithm

    Isao NAKANISHI  Yoshio ITOH  Yutaka FUKUI  

     
    LETTER-Digital Signal Processing

      Vol:
    E79-A No:11
      Page(s):
    1918-1921

    For reduction of computational complexity in the IA algorithm, the thinned-out IA algorithm in which only one step size is updated every iteration is proposed and is complementarily switched with the HA algorithm according to the convergence. The switching is determined by using the gradient of the error signal power. These are investigated through the computer simulations.

  • Cancellation Technique of Parasitic Poles for Active-R Highpass Filter

    Takao TSUKUTANI  Masaru ISHIDA  Yutaka FUKUI  

     
    LETTER-Analog Filters

      Vol:
    E74-A No:10
      Page(s):
    3083-3085

    This letter presents a cancellation technique of parasitic poles of operational amplifier (op amp) in active filter design. To minimize the effect of the parasitic poles, a three-pole model of op amp is utilized. A second order highpass filter is evaluated both theoretically and numerically.

  • Immittance Function Simulator Using a Single Current Conveyor

    Akinori HIMURA  Yutaka FUKUI  Masaru ISHIDA  Masami HIGASHIMURA  

     
    PAPER-Analog Signal Processing

      Vol:
    E72-E No:12
      Page(s):
    1279-1284

    Simulation circuits of grounded higher-order immittance element and immittance function using a single current conveyor are proposed. Simple filter structures with 2nd- and 3rd-order transfer function are realized by using the simulated immittance function. Circuit analysis for finding the desired simulator is carried out on computer using symbolic mathematics system.

  • On the Necessity of Estimating the Transfer Level in an Allpass-FIR ADF by the Use of Lyapunov Criteria

    James OKELLO  Shin'ichi ARITA  Yoshio ITOH  Yutaka FUKUI  Masaki KOBAYASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E83-A No:5
      Page(s):
    888-894

    In this paper we present an analysis based on the indirect Lyapunov criteria, that is used to study the convergence of an infinite impulse response (IIR) adaptive digital filter (ADF) based on estimation of the allpass system. The analysis is then extended to investigate the necessity of directly estimating the transfer level of the unknown system. We consider two cases of modeling the ADF. In the first system, the allpass section of the ADF estimates only the real poles of the unknown system while in the second system, both real and complex poles the allpass section are estimated. From the analysis and computer simulation, we realize that the poles of the ADF converge selectively to the poles of the unknown system, depending on the sign of the step size of adaptation. Using these results we proposed a new method to control the convergence of the poles the IIR ADF based on estimation of the allpass system.

  • Introduction of Orthonormal Transform into Neural Filter for Accelerating Convergence Speed

    Isao NAKANISHI  Yoshio ITOH  Yutaka FUKUI  

     
    LETTER

      Vol:
    E83-A No:2
      Page(s):
    367-370

    As the nonlinear adaptive filter, the neural filter is utilized to process the nonlinear signal and/or system. However, the neural filter requires large number of iterations for convergence. This letter presents a new structure of the multi-layer neural filter where the orthonormal transform is introduced into all inter-layers to accelerate the convergence speed. The proposed structure is called the transform domain neural filter (TDNF) for convenience. The weights are basically updated by the Back-Propagation (BP) algorithm but it must be modified since the error back-propagates through the orthogonal transform. Moreover, the variable step size which is normalized by the transformed signal power is introduced into the BP algorithm to realize the orthonormal transform. Through the computer simulation, it is confirmed that the introduction of the orthonormal transform is effective for speedup of convergence in the neural filter.

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