A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

A new common-bus architecture with temporal and spatial parallel access capabilities under wire-resource constraint is proposed to transfer vast quantities of data between modules inside a VLSI chip. Since bus controllers are distributed into modules, the proposed bus architecture can directly transfer data from one module to another without any central bus control unit like a Direct Memory Access (DMA) controller, which enables to reduce communication steps for data transfer between modules. Moreover, when a start address and the number of block data in both source/destination modules are determined at the first step of a data-transfer scheme, no additional address setting for the data transfer is required in the rest of the scheme, which allows us to use all the wire resources as only the "data bus." Therefore, the bus function is dynamically programmed, which results in achieving high throughput of bus communication. For example, in case of a 64-line common bus, it is evaluated that the maximum data throughput in the proposed architecture with dynamic bus-function programming is four times higher than that in the conventional DMA bus architecture with fixed 32-bit-address/32-bit-data buses.

A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width8.18 mm). To the authors' knowledge, these RF power performances with high linear gain are the best data at 12 GHz.

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

An energy-efficient intra-chip communication link circuit with ternary current signaling is proposed for an asynchronous Network-on-Chip. The data signal encoded by an asynchronous three-state protocol is represented by a small-voltage-swing three-level intermediate signal, which results in the reduction of transition delay and achieving energy-efficient data transfer. The three-level voltage is generated by using a combination of dynamically controlled current sources with feedback loop mechanism. Moreover, the proposed circuit contains a power-saving scheme where the dynamically controlled transistors also are utilized. By cutting off the current paths when the data transfer on the communication link is inactive, the power dissipation can be greatly reduced. It is demonstrated that the average data-transfer speed is about 1.5 times faster than that of a binary CMOS implementation using a 130nm CMOS technology at the supply voltage of 1.2V.

A tunneling magnetoresistive(TMR)-based logic-in- memory circuit, where storage functions are distributed over a logic-circuit plane, is proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability, any logic functions with external inputs and stored inputs can be performed by using the TMR-based resistor/transistor network. The combination of dynamic current-mode circuitry and a TMR-based logic network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of an SAD unit for MPEG encoding is discussed, and its advantages are demonstrated.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).

A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18- µm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500 MHz.