We have developed a power amplifier IC for Bluetooth Class 1 operating at single low voltage of 1.8 V for both control and drain voltages. We can realize it due to fully enhancement-mode hetero-junction FETs utilizing a re-grown p +-GaAs gate technology. The power amplifier is a highly compact design as a small package of 1.5 mm1.5 mm0.4 mm with fully integrated gain control and shutdown functions. An impressive power added efficiency of 52% at an output power of 20 dBm is achieved with an associated gain of 22 dB. Also, sufficiently low leakage current of 0.25 µA at 27 is exhibited, which is comparable to conventional HBT power amplifiers.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.

Wide-band CDMA (W-CDMA) distortion characteristics of a fabricated double-doped heterojunction FET (HJFET) are presented. Measured results demonstrate that the first and second adjacent channel W-CDMA adjacent channel leakage power ratios (ACPRs) of the HJFET are correlated to the third- and fifth-order intermodulation (IM3 and IM5) distortions respectively under various quiescent drain current operation (Iq). A first channel ACPR dip phenomenon is observed under a low Iq condition, resulting in improved power added efficiency. Due to its close correlation to the IM3 distortion, the ACPR dip phenomenon is explained in terms of the similar IM3 characteristic. Simulated results reveal that the dip is a consequence of the cancellation of distortions generated by the third- and fifth-order nonlinearities at the IM3 frequency. The conditions for the cancellation are detailed.

This report presents Dual Field-modulating-Plates (Dual-FP) technology for a 28 V operated high power GaAs heterojunction FET (HJFET) amplifier. A developed HJFET has two FP electrodes; the 1st-FP is connected to the gate and the 2nd-FP to the ground. The 2nd-FP suppresses the drain current dispersion effectively cooperating with the 1st-FP, and it can also reduce the gate-drain parasitic capacitance. The developed push-pull amplifier, with four Dual-FPFET chips, demonstrated 55.1 dBm (320 W) output power with a 14.0 dB linear gain and a drain efficiency of 62% at 2.14 GHz. Under two-carrier W-CDMA signals, it showed a high drain efficiency of 30% and low third-order Inter-modulation distortion of -37 dBc at output power of 47.5 dBm.

This paper describes 1.0 V operation power performance of a double doped AlGaAs/InGaAs/AlGaAs heterojunction FET for personal digital cellular phones. The developed FET with a multilayer cap consisting of a highly Si-doped GaAs, an undoped GaAs and a highly Si-doped AlGaAs exhibited an on-resistance of 1.3 Ωmm and a maximum drain current of 620 mA/mm. A 28 mm gate-width device, operating with a drain bias voltage of 1.0 V, demonstrated an output power of 1.0 W, a power-added efficiency of 59% and an associated gain of 13.7 dB at an adjacent channel leakage power at 50 kHz off-center frequency of -48 dBc with a 950 MHz π/4-shifted quadrature phase shift keying signal.

A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width8.18 mm). To the authors' knowledge, these RF power performances with high linear gain are the best data at 12 GHz.