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[Author] Yasunori BITO(3hit)

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  • 1.0 V Operation Power Heterojunction FET for Digital Cellular Phones

    Takehiko KATO  Yasunori BITO  Naotaka IWATA  

     
    PAPER-Microwaves, Millimeter-Waves

      Vol:
    E84-C No:2
      Page(s):
    249-252

    This paper describes 1.0 V operation power performance of a double doped AlGaAs/InGaAs/AlGaAs heterojunction FET for personal digital cellular phones. The developed FET with a multilayer cap consisting of a highly Si-doped GaAs, an undoped GaAs and a highly Si-doped AlGaAs exhibited an on-resistance of 1.3 Ωmm and a maximum drain current of 620 mA/mm. A 28 mm gate-width device, operating with a drain bias voltage of 1.0 V, demonstrated an output power of 1.0 W, a power-added efficiency of 59% and an associated gain of 13.7 dB at an adjacent channel leakage power at 50 kHz off-center frequency of -48 dBc with a 950 MHz π/4-shifted quadrature phase shift keying signal.

  • 1.8 V Operation Power Amplifier IC for Bluetooth Class 1 Utilizing p+-GaAs Gate Hetero-Junction FET

    Fumio HARIMA  Yasunori BITO  Hidemasa TAKAHASHI  Naotaka IWATA  

     
    PAPER-GaAs- and InP-Based Devices

      Vol:
    E91-C No:7
      Page(s):
    1104-1108

    We have developed a power amplifier IC for Bluetooth Class 1 operating at single low voltage of 1.8 V for both control and drain voltages. We can realize it due to fully enhancement-mode hetero-junction FETs utilizing a re-grown p +-GaAs gate technology. The power amplifier is a highly compact design as a small package of 1.5 mm1.5 mm0.4 mm with fully integrated gain control and shutdown functions. An impressive power added efficiency of 52% at an output power of 20 dBm is achieved with an associated gain of 22 dB. Also, sufficiently low leakage current of 0.25 µA at 27 is exhibited, which is comparable to conventional HBT power amplifiers.

  • Single 1. 5 V Operation Power Amplifier MMIC with SrTiO3 Capacitors for 2. 4 GHz Wireless Applications

    Takeshi B. NISHIMURA  Naotaka IWATA  Keiko YAMAGUCHI  Masatoshi TOMITA  Yasunori BITO  Koichi TAKEMURA  Yoichi MIYASAKA  

     
    PAPER-Semiconductor Devices and Amplifiers

      Vol:
    E81-C No:6
      Page(s):
    898-903

    This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.