IEICE TRANSACTIONS on Electronics
Step-Recessed Gate Structure with an Undoped Surface Layer for Microwave and Millimeter-Wave High Power, High Efficiency GaAs MESFETs
Summary :
A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.12 pp.4141-4146
- Publication Date
- 1991/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Millimeter-Wave/Heterojunction Devices)
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Hidemasa TAKAHASHI, Kazunori ASANO, Kouji MATSUNAGA, Naotaka IWATA, Akira MOCHIZUKI, Hiromitsu HIRAYAMA, "Step-Recessed Gate Structure with an Undoped Surface Layer for Microwave and Millimeter-Wave High Power, High Efficiency GaAs MESFETs" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 12, pp. 4141-4146, December 1991, doi: .
Abstract: A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_12_4141/_p
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@ARTICLE{e74-c_12_4141,
author={Hidemasa TAKAHASHI, Kazunori ASANO, Kouji MATSUNAGA, Naotaka IWATA, Akira MOCHIZUKI, Hiromitsu HIRAYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Step-Recessed Gate Structure with an Undoped Surface Layer for Microwave and Millimeter-Wave High Power, High Efficiency GaAs MESFETs},
year={1991},
volume={E74-C},
number={12},
pages={4141-4146},
abstract={A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Step-Recessed Gate Structure with an Undoped Surface Layer for Microwave and Millimeter-Wave High Power, High Efficiency GaAs MESFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 4141
EP - 4146
AU - Hidemasa TAKAHASHI
AU - Kazunori ASANO
AU - Kouji MATSUNAGA
AU - Naotaka IWATA
AU - Akira MOCHIZUKI
AU - Hiromitsu HIRAYAMA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1991
AB - A new structure GaAs power FET was designed and fabricated for high output power with sufficiently high efficiency. The undoped surface layer was introduced to achieve simultaneous increase in the maximum channel current (Imax) and the gate drain breakdown voltage (BVgd) under the large signal RF conditions. In addition the step-recessed gate structure was adopted and optimized to attain a high breakdown voltage and a high linear gain by using the two dimensional device simulator. A high fmax of 65 GHz was obtained at the "class-A" mode bias point, with the 0.55 µm gate length. The maximum fmax of 91 GHz was obtained. The test device feasibility was tested at 12 GHz and the output power/efficiency characteristics of 4.0 W/40.1% with the gain of 9.2 dB have been achieved in the "class-A" mode operation for a single chip (gate width
ER -
English
