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[Author] Yuma WATANABE(2hit)

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  • System Status Aware Hadoop Scheduling Methods for Job Performance Improvement

    Masatoshi KAWARASAKI  Hyuma WATANABE  

     
    PAPER-Fundamentals of Information Systems

      Pubricized:
    2015/03/26
      Vol:
    E98-D No:7
      Page(s):
    1275-1285

    MapReduce and its open software implementation Hadoop are now widely deployed for big data analysis. As MapReduce runs over a cluster of massive machines, data transfer often becomes a bottleneck in job processing. In this paper, we explore the influence of data transfer to job processing performance and analyze the mechanism of job performance deterioration caused by data transfer oriented congestion at disk I/O and/or network I/O. Based on this analysis, we update Hadoop's Heartbeat messages to contain the real time system status for each machine, like disk I/O and link usage rate. This enhancement makes Hadoop's scheduler be aware of each machine's workload and make more accurate decision of scheduling. The experiment has been done to evaluate the effectiveness of enhanced scheduling methods and discussions are provided to compare the several proposed scheduling policies.

  • Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

    Akira MOCHIZUKI  Hirokatsu SHIRAHAMA  Yuma WATANABE  Takahiro HANYU  

     
    PAPER-Communication for VLSI

      Vol:
    E97-D No:9
      Page(s):
    2304-2311

    An energy-efficient intra-chip communication link circuit with ternary current signaling is proposed for an asynchronous Network-on-Chip. The data signal encoded by an asynchronous three-state protocol is represented by a small-voltage-swing three-level intermediate signal, which results in the reduction of transition delay and achieving energy-efficient data transfer. The three-level voltage is generated by using a combination of dynamically controlled current sources with feedback loop mechanism. Moreover, the proposed circuit contains a power-saving scheme where the dynamically controlled transistors also are utilized. By cutting off the current paths when the data transfer on the communication link is inactive, the power dissipation can be greatly reduced. It is demonstrated that the average data-transfer speed is about 1.5 times faster than that of a binary CMOS implementation using a 130nm CMOS technology at the supply voltage of 1.2V.