IEICE TRANSACTIONS on Information
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
Summary :
This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).
- Publication
- IEICE TRANSACTIONS on Information Vol.E97-D No.6 pp.1546-1556
- Publication Date
- 2014/06/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E97.D.1546
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Naoya ONIZAWA
Tohoku University
Akira MOCHIZUKI
Tohoku University
Hirokatsu SHIRAHAMA
Tohoku University
Masashi IMAI
Hirosaki University
Tomohiro YONEDA
National Institute of Informatics
Takahiro HANYU
Tohoku University
Keyword
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Naoya ONIZAWA, Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Masashi IMAI, Tomohiro YONEDA, Takahiro HANYU, "High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 6, pp. 1546-1556, June 2014, doi: 10.1587/transinf.E97.D.1546.
Abstract: This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E97.D.1546/_p
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@ARTICLE{e97-d_6_1546,
author={Naoya ONIZAWA, Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Masashi IMAI, Tomohiro YONEDA, Takahiro HANYU, },
journal={IEICE TRANSACTIONS on Information},
title={High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs},
year={2014},
volume={E97-D},
number={6},
pages={1546-1556},
abstract={This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).},
keywords={},
doi={10.1587/transinf.E97.D.1546},
ISSN={1745-1361},
month={June},}
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TY - JOUR
TI - High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
T2 - IEICE TRANSACTIONS on Information
SP - 1546
EP - 1556
AU - Naoya ONIZAWA
AU - Akira MOCHIZUKI
AU - Hirokatsu SHIRAHAMA
AU - Masashi IMAI
AU - Tomohiro YONEDA
AU - Takahiro HANYU
PY - 2014
DO - 10.1587/transinf.E97.D.1546
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2014
AB - This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause data-transmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 µm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (<10-20).
ER -
English
