IEICE TRANSACTIONS on Electronics
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic
Summary :
A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1591-1597
- Publication Date
- 2006/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.11.1591
- Type of Manuscript
- Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
- Category
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Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU, "Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 11, pp. 1591-1597, November 2006, doi: 10.1093/ietele/e89-c.11.1591.
Abstract: A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1591/_p
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@ARTICLE{e89-c_11_1591,
author={Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic},
year={2006},
volume={E89-C},
number={11},
pages={1591-1597},
abstract={A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.},
keywords={},
doi={10.1093/ietele/e89-c.11.1591},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1591
EP - 1597
AU - Akira MOCHIZUKI
AU - Hirokatsu SHIRAHAMA
AU - Takahiro HANYU
PY - 2006
DO - 10.1093/ietele/e89-c.11.1591
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.
ER -
English
