This letter presents a novel method to design a power distribution network with highly accurate impedance characteristic. Based on the PBEC (path-based equivalent circuit) model and the network synthesis, the proposed design method exploits simple arithmetic expressions to calculate the electrical parameters of a power distribution network. It directly calculates and determines the size of on-chip decoupling capacitors, the size and location of off-chip decoupling capacitors, and the effective inductances of the package power bus. To evaluate the accuracy of the proposed method, it was applied to a test board with size of 12.5 cm 12.5 cm and with plane-to-plane distance of 200 µm. The proposed method successfully designed a power distribution network keeping its impedance characteristic under 1 Ω with frequency range of 100 kHz-1 GHz. The proposed design method requires negligible computation when compared with conventional PEEC (partial elements equivalent circuit) model-based design approaches, but the simulation results of both methods are almost identical. Consequently, the proposed method enables simple, fast and accurate design of power-distribution networks, which gives economic and practical solutions for commercial tools.

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 µm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 µm Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 µm standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstcase design environment improves optimization speed by 29.61-32.01% compared to that of the conventional worstcase optimization. The new statistical interconnect worstcase design environment accurately predicts the worstcase and bestcase corners of non-normal distribution where conventional methods cannot do well.

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeley's 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6 V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeley's 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 µm CMOS technology, 0.13 µm IBM CMOS technology and Berkeley's 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

This paper proposes a novel extraction method of line parameters for multi-coupled lines on high-speed and high-density PCBs, where it uses TDR measurement in time domain and S-parameter measurement in frequency domain. The accuracy of the proposed method have been verified experimentally by comparing the crosstalk noise in the time domain, where (1) the proposed method extracts RLGC matrices by measuring the test pattern, (2) the crosstalk noise is obtained through SPICE simulation using the extracted RLGC matrices, and (3) the SPICE-simulated crosstalk noise is compared with the measured crosstalk noise. From the crosstalk noise comparison, the proposed method is proven to be very accurate. For N-coupled lines, the proposed method doesn't require expensive 2N-port probe for N-coupled lines but only two-port probe, which provides a simple, accurate, and economic extraction method of line parameters for multi-coupled line on the PCB. In the early stage of PCB design, the proposed method is very useful, because it extracts accurate interconnection parameters of each test board and enables to compensate various side effects due to the variation of PCB fabrication process. Also, the proposed method is necessary to analyze the signal integrity of future high-density and high-speed digital system on PCBs.

We suggest a novel digitally-controlled SMPS using a high-resolution DPWM generator. In the proposed circuit, the duty ratio of the DPWM is determined by the voltage slope control of an internal capacitor using a pseudo relaxation-oscillation technique. This new control method has a simpler structure, and consumes less power compared to a conventional digitally-controlled SMPS. Therefore, the proposed circuit is able to operate at a high switching frequency (1 MHz10 MHz) obtained from a relatively low internal operating frequency (10 MHz100 MHz) with a small area. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit, including the output buffer driver, is 15 mA at 10 MHz switching frequency. The proposed circuit is designed to supply a maximum 1A with maximum DPWM duty ratio of 90%. The output voltage ripple is 7 mV at 3.3 V output voltage. To verify the operation of the proposed circuit, we performed a simulation with Dongbu Hitek BCD 0.35 µm technology.

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

In this paper, we propose new low-hardware-cost motion estimation with a large search range for VLSI multimedia processors. It reduces the hardware amount required for pixel comparison by reducing both the spatial-resolution and bit-resolution of pixel values. Low-hardware-cost block-matching criterion is also employed. To avoid performance degradation from low resolution, we introduce an "outlier" pixel with large overload quantization error in the search window, and a search position is excluded from the motion estimation if its corresponding search window block contains one or more outliers. The proposed motion estimation is easy to implement in VLSI multimedia processors, and it significantly reduces the hardware amount when the search range is larger than 6464. In MPEG2 MP@ML video compression with 128128 search range, it reduces the hardware cost to 1/144 that of the full search algorithm, while its degradation of peak signal-to-noise ratio is 0.32 dB.

Block-wise shutdown of idle functional blocks in VLSI systems is a promising approach to reduce power consumption. Especially, multi-threshold voltage CMOS (MTCMOS) is widely accepted to save leakage power during idle time. As operating frequency increases, it requires short wake-up time to use the shutdown block in time. However, short wake-up time of a large block causes large current surge during wake-up process. This often leads to system malfunction due to severe power line noise. This is one of the serious problems for practical implementation of MTCMOS block-wise shutdown. This letter proposes an effective wake-up scheme for block-wise shutdown of low-power VLSI systems. It exploits pipelined wake-up strategy that reduces current surge during wake-up process. In this letter, the proposed scheme was analyzed and simulated from the viewpoint of power distribution network. To verify its validity, it was applied to a multiplier block in Compact Flash controller chip on a test board. According to the simulation results of equivalent R, L, and C modeling, the proposed scheme achieved significant improvement over conventional concurrent shutdown schemes.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.