A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

A cross-coupled charge pump with internal pumping capacitor, which is advantageous from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using NMOS and PMOS diodes connected to boosting nodes from VIN nodes, the pumping node is precharged to the same value at the pumping node in starting pumping. Since the first-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located in front of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with the conventional cross-coupled charge pump by using a stack-MIM capacitor. A proposed charge pump for TFT-LCD driver IC is designed with 0.13 µm triple-well DDI process, fabricated, and tested.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18 µm BCD process is 283.565524.180 µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18 µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1 V less than that of the p+ gate poly-silicon.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.

We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52495.78 µm2.

A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.