IEICE TRANSACTIONS on Electronics
Efficient and Large-Current-Output Boosted Voltage Generators with Non-Overlapping-Clock-Driven Auxiliary Pumps for Sub-1-V Memory Applications
Summary :
A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.7 pp.1208-1213
- Publication Date
- 2004/07/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
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Kyeong-Sik MIN, Young-Hee KIM, Daejeong KIM, Dong Myeong KIM, Jin-Hong AHN, Jin-Yong CHUNG, "Efficient and Large-Current-Output Boosted Voltage Generators with Non-Overlapping-Clock-Driven Auxiliary Pumps for Sub-1-V Memory Applications" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 7, pp. 1208-1213, July 2004, doi: .
Abstract: A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_7_1208/_p
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@ARTICLE{e87-c_7_1208,
author={Kyeong-Sik MIN, Young-Hee KIM, Daejeong KIM, Dong Myeong KIM, Jin-Hong AHN, Jin-Yong CHUNG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Efficient and Large-Current-Output Boosted Voltage Generators with Non-Overlapping-Clock-Driven Auxiliary Pumps for Sub-1-V Memory Applications},
year={2004},
volume={E87-C},
number={7},
pages={1208-1213},
abstract={A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - Efficient and Large-Current-Output Boosted Voltage Generators with Non-Overlapping-Clock-Driven Auxiliary Pumps for Sub-1-V Memory Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 1208
EP - 1213
AU - Kyeong-Sik MIN
AU - Young-Hee KIM
AU - Daejeong KIM
AU - Dong Myeong KIM
AU - Jin-Hong AHN
AU - Jin-Yong CHUNG
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2004
AB - A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.
ER -
English
