In this letter, a novel association method called ELBA (efficient load balancing association) is proposed for improved load balancing in IEEE 802.15.4-based WSNs (wireless sensor networks). ELBA adds new nodes to the network in an efficient load-balancing manner by exploiting not only RSSI (received signal strength indicator), which is used in the standard, but also traffic-load, the number of allocated GTSs (guaranteed time slots), and the number of parent nodes and child nodes. Simulation results show that ELBA offers better performance in load balancing and preventing congestion.

We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18 µm BCD process is 283.565524.180 µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18 µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1 V less than that of the p+ gate poly-silicon.

We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52495.78 µm2.