An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

A composite right/left-handed (CRLH) transmission line with demultiplexing property is proposed towards short-range functional wireless interconnects. The CRLH line is designed by analyzing dispersion relation of the microstrip line having a split-ring and a double-stub structure to realize frequency selective properties for leaky wave radiation. A prototype device is fabricated and estimated to study feasibility of the demultiplexing operation around ten GHz.

A single flux quantum (SFQ) logic cell library has been developed for the 10 kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm2 to 10 kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because SFQ circuits work by pulse logic while CMOS circuits work by level logic. In this paper, we compare implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits. We show that a set of individual bit-serial adders and Kogge-Stone adder are superior to others.

We have been studying a superconducting quantum-computing system where superconducting qubits are controlled and read out by rapid single-flux- quantum (RSFQ) circuits. In this study, we designed and fabricated an RSFQ microwave chopper, which turns on and off an externally applied microwave to control qubit states with the time resolution of sub-nanosecond. The chopper is implemented in a microwave module and mounted in a dilution refrigerator. We tested the microwave chopper at 4.2 K. The amplitude of the output microwave was approximately 100 µV which is much larger than that of previously designed chopper. We also confirmed that the irradiation time can be controlled by RSFQ control circuits.

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40 GHz for an automatically routed 44 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.

A physical random number generator, which generates truly random number trains by using the randomness of physical phenomena, is widely used in the field of cryptographic applications. We have developed an ultra high-speed superconductive physical random number generator that can generate random numbers at a frequency of more than 10 GHz by utilizing the high-speed operation and high-sensitivity of superconductive integrated circuits. In this study, we have statistically evaluated the quality of the random number trains generated by the superconductive physical random number generator. The performances of the statistical tests were based on a test method provided by National Institute of Standards and Technology (NIST). These statistical tests comprised several fundamental tests that were performed to evaluate the random number trains for their utilization in practical cryptographic applications. We have generated 230 random number trains consisting of 20,000-bits by using the superconductive physical random number generator fabricated by the SRL 2.5 kA/cm2 Nb standard process. The generated random number trains passed all the fundamental statistical tests. This result indicates that the superconductive random number generator can be sufficiently utilized in practical applications.

A physics-based equivalent circuit model of the ceramic capacitor is proposed, which can reproduce frequency characteristics of its impedance including the often observed yet hitherto physically unexplained kinks appearing above the primary series resonance frequency. The model can also account for parasitic effects of external inductances. In order to efficiently analyze and gain engineering insight into ceramic capacitors with a large number of metallic laminae, a two-dimensional method of moments is developed that treats the laminar structure as a uniform, effective medium. It turns out that the primary resonance and the kinks can be well understood and modeled by a lossy transmission line stub with a drastic wavelength reduction. The capacitor model is completed by adding components describing the skin effect and external inductances. The modeled impedance stays within a 4% margin of error up to 5 GHz. The proposed model could greatly improve the accuracy of power distribution network simulation.

Memristor is drawing more and more attraction nowadays after HP Laboratory announced its invention. Since then many researchers are taking efforts to find its applications in various areas of the information technology. Among the important applications, one of the interesting issues is the research on memristor circuits. To put forward such research, there is an urgent demand to establish a memristor SPICE model, such that people could conduct SPICE simulation to obtain the performance of the memristor circuits under their investigation. This paper reports our efforts to meet the urgent demand. Based on the memristor device fabrication technology parameters, as well as the theoretical description on memristor, we first propose memristor SPICE models, then verify the effectiveness of the proposed models by applying it to some memristor circuits. Simulation results are satisfactory.

An inverter is a circuit which outputs ¬ x1, ¬ x2, ..., ¬ xn for any Boolean inputs x1, x2, ..., xn. We consider constructing an inverter with AND gates and OR gates and a few NOT gates. Beals, Nishino and Tanaka have given a construction of an inverter which has size O(nlog n) and depth O(log n) and uses ⌈ log (n+1) ⌉ NOT gates. In this paper we give a construction of an inverter which has size O(n) and depth log 1+o(1)n and uses log 1+o(1)n NOT gates. This is the first negation-limited inverter of linear size using only o(n) NOT gates. We also discuss implications of our construction for negation-limited circuit complexity.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

A CMOS current-mode nth-switchable-root circuit composed of a compact logarithm circuit, a divide-by-n circuit, and a compact exponential circuit is proposed. The n can be selected from 5 values by three switches. Simulation results indicate that the compact nth-switchable-root circuit has a wide input-current range for relative errors less than 3%, low power dissipations below 630 µW, and high bandwidth over 330 MHz.

This paper presents a design of a monolithic transformer using bond wires. The proposed transformer structure has several advantages such as high power handling and high efficiency. It shows that the measured insertion loss at the 1.9 GHz range is -1.54 dB (70%), which is higher than the spiral transformer of the same size. Also, it shows a phase error of less than 1 degree.

This paper presents a numerical approach to the time-domain analysis of N-branch-line couplers. The approach is based on the modified central difference (MCD) method combined with internal boundary treatments, which consist of the time-domain scattering matrix for the three-port junction discontinuity. The behavior of the signal propagation including multiple reflections on the N-branch-line coupler with and without line loss is analyzed and demonstrated in the time domain. Additionally, the S-parameters obtained from Gaussian pulse responses of the N-branch-line directional couplers are shown. The simulated results are in good agreement with those of the commercial simulator.

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3 dB with gain error of less than 0.38 dB. The IIP3, P1 dB, and smallest 3-dB bandwidth are 10.5 to 27 dBm, -9 to 9.5 dBm, and 250 MHz, respectively. The PGA occupies the chip area of 0.04 mm2 and consumes only 460 µA from a 1.2 V supply.

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.

An improved nonlinear circuit model for a GaAs Gunn diode in an oscillator is proposed based on the physical mechanism of the diode. This model interprets the nonlinear harmonic character on the Gunn diode. Its equivalent nonlinear circuit of which can assist in the design of the Gunn oscillator and help in the analysis of the fundamental and harmonic characteristics of the GaAs Gunn diode. The simulation prediction and the experiment of the Gunn oscillator show the feasibility of the nonlinear circuit model for the GaAs Gunn oscillator.

Our paper proposes a low power delay element with many other valuable characteristics for asynchronous circuits in the bundled-data implementation. Delay elements are frequently utilized to interact with asynchronous environment for revealing the current status of the bundled-data asynchronous circuits. Thus, a notable portion of the total energy is consumed by the delay elements for this kind of designs. Moreover, constructing a specific delay on a chip is a difficult task for recent CMOS technology. An extreme low power asymmetrical delay element with post-chip adjustment feature was developed mainly for solving these issues. Our initial intention was to develop a programmable delay element for asynchronous data path components. The proposed delay element is also suitable for many other applications requiring low power constraint. In addition to the programmability, the delay element also demonstrated efficiently characteristics such as good tolerance to process and temperature variations on the delay. Our delay element is equivalent to approximately the average power of a 4-stage inverter chain. A large delay can be obtained by cascaded scheme with nearly zero handshaking overhead. All arguments were cautiously verified by the post-layout simulation setup using TSMC 0.35 µm and 0.18 µm technologies under all extreme corners.