This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.

Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa2Cu3O7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (Ic) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than 7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360 GHz at 4.2 K and 210 GHz at 41 K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10-6.

Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p+/n+ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p+/n+ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5 GHz bandwidth, that was formed in a 0.25-µm CMOS high frequency.

Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation and experimental results show that the proposed band connections reduce the noise.

This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20-100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.

The crosstalk phenomenon, wich occurs between transmission lines, is caused by electromagnetic fields of currents flowing through the lines. Crosstalk between two bent lines is studied by using a set of solutions of modified telegrapher's equations. By expressing electromagnetic fields in terms of voltages and currents in the line ends, the resultant network function in the form of an ABCD matrix is obtained. Electromagnetic fields caused by currents flowing in risers at transmission line ends are taken into account in addition to those fields in line sections. The validity of the proposed approach was confirmed by comparing experimental results with computed results and those simulated by a commercial electromagnetic solver for some bent-line models.

We propose a protocol for implementing secure circuit evaluation (SCE) based on the threshold homomorphic ElGamal encryption scheme and present the implementation results of the protocol. To the best of knowledge of the authors, the proposed protocol is more efficient in terms of computational complexity than previously reported protocols. We also introduce applications using SCE and estimate their practicality based on the implementation results.

We fabricated various microscopic optical devices with Si photonic wire waveguides and demonstrated their fundamental characteristics. The bending loss of the waveguide was practically negligible when the bending radius of the waveguide exceeded 5 µm. Therefore, we can fabricate very compact optical devices with the waveguide. We demonstrated an optical directional coupler with the waveguide. The coupling length of the directional coupler was extremely small, several micrometers, because of strong optical coupling between the waveguide cores. We also demonstrated ultrasmall optical add/drop multiplexers (OADMs) with Bragg grating reflectors constructed from the waveguides. The dropping wavelength bandwidth of the OADM device was less than 2 nm and the dropping center wavelength could be tuned using thermooptic control with a microheater formed on the Bragg reflector. Using the Si photonic wire waveguide, we also demonstrated thermooptic switches by forming a microheater on a branch of a Mach-Zehnder interferometer made up of the waveguides. In this switching operation, we observed an extinction ratio exceeding 30 dB, a switching power less than 90 mW, and a switching response speed less than 100 µs using a 12 optical switch with an 8530 µm2 footprint.

This paper introduces a new graph problem to find an Optimal Euler Circuit (OEC) in an Euler graph. OEC is defined as the Euler circuit that maximizes the sum of contiguous costs along it, where the contiguous cost is assigned for each of the two contiguous edges incident to a vertex. We prove that the OEC problem is NP-complete. A polynomial time algorithm will be presented for the case of a graph without vertex of degree greater than 4, and for the general case, a 1/4-approximation polynomial time algorithm will be proposed.

A broadband microstrip-to-waveguide transition is developed in the millimeter-wave band. No additional parts and complicated structures are needed to extend the frequency bandwidth. Only the simple and novel geometrical features are added in the printed pattern on the substrate. The proposed transition operates over a quite broad frequency bandwidth due to its double resonance. The two resonant frequencies are controlled by adjusting dimensions of the structure according to the required bandwidth, the reflection level and the center frequency. Two versions of the transition are designed and reliability is confirmed by experiments in the millimeter-wave band. The design frequency is 76.5 GHz. Bandwidth 12.9 GHz (16.8%) is obtained where the reflection level is lower than -30 dB. In the other design for broadband, the bandwidth for reflection level lower than -20 dB results in 24.9 GHz (32.5%). Furthermore, it is confirmed in the experiment and simulation that the center frequency is controlled from 75.3 GHz to 78.7 GHz by changing the geometry of the printed pattern.

In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.

This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.

This paper presents a method for synthesizing a coherent 1-input 3-output optical delay-line circuit with N stages that is composed of 2(N + 1) directional couplers, N optical delay-lines, 2(N + 1) phase shifters and one external phase shifter with phase value φc . The path difference is equal to the delay time difference Δτ. Synthesis algorithm is based on the division of the transfer matrix into basic component transfer matrices and factorization is completed by repeated size-reduction. A set of recursion equations are also defined to obtain the unknown circuit parameters. In the developed method, it is shown that (13) optical delay-line circuit has the same transmission characteristics as finite impulse response (FIR) digital filters with complex expansion coefficients. Band-pass flat group delay type filter is considered as an example in this paper. It is also confirmed that developed (13) optical delay-line circuit can realize 100% power transmittance.

This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algorithm analyzes the pipelined circuit and determines the intermediate registers that can be removed. An efficient subsidiary algorithm is presented that computes the minimum feasible clock period of a circuit containing multi-clock cycle paths. Experiments with a pipelined adder and multiplier verify that the proposed algorithm can reduce the number of intermediate registers without degrading performance, even when delay variations exist.

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.