In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].

This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

This paper describes the design and development of a module generator for a dual-rail PLA with embedded 2-input logic cells for 0.35 µm CMOS technology. In order to automatically generate logic-cell based PLA layouts from circuit specifications, a module generator as a design automation tool of logic-cell based PLA is developed with a structural improvement. This module generator is based on a timing-driven design methodology and consists of logic synthesis, transistor sizing and logic cell generation, stimulus generation, HDL model generation parts. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. The layout is generated by using 0.35 µm, 3-metal-layer CMOS technology. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters. The design complexity which is becoming an important issue for VLSI circuits can be reduced partially and human caused errors are minimized by module generator. A PLA layout in GDS-II form and an HDL model behavior of a Boolean function which has 64-bit input, 1-bit output and 220 product term can be generated within 8 minutes on a SunUltraSPARC-III 900 MHz processor. A very short time is required to compile the module, and this makes it feasible for designers to try many different design configurations in order to get the better one.

This paper describes an area-efficient dual-rail array logic architecture, a logic-cell-embedded PLA (LCPLA), which has 2-input logic cells in the structure. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA. The logic cells can be designed by connecting some local wires and do not require additional transistors over logic cells of the conventional dual-rail PLA. By using the logic cells, some classes of logic functions can be implemented efficiently, so that high-speed and low-power operations are also achieved. The advantages over the conventional PLAs and standard-cell-based designs were demonstrated by using benchmark circuits, and the LCPLA is shown to be effective to reduce the number of product terms. In a structure with a 64-bit input and a 1-bit output including 220 product terms, the LCPLA achieved an area reduction by 35% compared to the conventional high-speed dual-rail PLA, and the power-delay product was reduced by 74% and 46% compared to the conventional high-speed single-rail PLA and the conventional high-speed dual-rail PLA, respectively. A test chip of this configuration was fabricated using a 0.35-µm, 3-metal-layer CMOS technology, and was verified with a functional test using a logic tester and an electron-beam tester at frequencies of up to 100 MHz with a supply voltage of 3.3 V.

With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.