IEICE TRANSACTIONS on Fundamentals
An Energy-Efficient Patchable Accelerator and Its Design Methods
Summary :
With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.12 pp.2507-2517
- Publication Date
- 2014/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.2507
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
Authors
Hiroaki YOSHIDA
Fujitsu Laboratories of America
Masayuki WAKIZAKA
Graduate School of Ritsumeikan University
Shigeru YAMASHITA
Graduate School of Ritsumeikan University
Masahiro FUJITA
The University of Tokyo
Keyword
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Hiroaki YOSHIDA, Masayuki WAKIZAKA, Shigeru YAMASHITA, Masahiro FUJITA, "An Energy-Efficient Patchable Accelerator and Its Design Methods" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 12, pp. 2507-2517, December 2014, doi: 10.1587/transfun.E97.A.2507.
Abstract: With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.2507/_p
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@ARTICLE{e97-a_12_2507,
author={Hiroaki YOSHIDA, Masayuki WAKIZAKA, Shigeru YAMASHITA, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Energy-Efficient Patchable Accelerator and Its Design Methods},
year={2014},
volume={E97-A},
number={12},
pages={2507-2517},
abstract={With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.},
keywords={},
doi={10.1587/transfun.E97.A.2507},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - An Energy-Efficient Patchable Accelerator and Its Design Methods
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2507
EP - 2517
AU - Hiroaki YOSHIDA
AU - Masayuki WAKIZAKA
AU - Shigeru YAMASHITA
AU - Masahiro FUJITA
PY - 2014
DO - 10.1587/transfun.E97.A.2507
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2014
AB - With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.
ER -
English
