We have proposed a tunable laser with silica-waveguide ring resonators. In this tunable laser, a semiconductor optical amplifier was passively aligned and mounted onto a silica-waveguide substrate. The ring resonators can be tuned by controlling their temperatures using the thermo optic heaters formed on them, and there are no mechanically moving parts. Thus, they are sufficiently stable and reliable for practical use. Our tunable laser exhibits a high fiber-output power of more than 15 dBm and a wide tunable range of 60 nm (L-band, 50 GHz spacing, 147 channels). Moreover, a tunable laser with a much wider tunable range of 96 nm using 100-GHz-FSR ring resonators is also reported.

The authors present R2Power, an effective approach to the realizable reduction of RC networks with independent current sources. The proposed approach is based on the entrywise perturbation theory for diagonally dominant M-matrices. The accuracy of the node voltages of the reduced network, as compared to those of the original network, is maintained on the order of the entrywise perturbation performed during reduction. R2Power can be used to reduce the size of RC networks used to model the power networks of SoCs, for efficient IR-drop analysis. Experiments showed that R2Power reduced the size of industrial examples by more than 95%, with maximum relative node voltage errors of less than 0.012%.

A new acceleration scheme that decreases the number of required iterations in relaxation methodology is proposed. The proposed scheme uses dynamic error prediction of an improved approximation to the solution during an iterative computation. The proposed scheme's application to circuit simulations required an average of 67.3% fewer iterations compared to un-accelerated relaxation methods.

This paper reviews our recent progress on arrayed waveguide gratings (AWGs) using super-high-Δ silica-based planar lightwave circuit (PLC) technology and their application to integrated optical devices. Factors affecting the chip size of AWGs and the impact of increasing relative index difference Δ on the chip size are investigated, and the fabrication result of a compact athermal AWG using 2.5%-Δ silica-based waveguides is presented. As an application of super-high-Δ AWGs to integrated devices, a flat-passband multi/demultiplexer consisting of an AWG and cascaded MZIs is presented.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

We identify a broadband equivalent circuit of an on-chip self-complementary antenna integrated with a µm-sized semiconductor mesa structure whose circuit elements can be interpreted by using closed-form analysis. Prior to the equivalent circuit analysis, an electromagnetic simulation is done to investigate frequency independency of the input impedance for the integrated self-complementary antenna in terahertz range.

A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.

An efficient and practical algorithm is proposed for finding all DC solutions of nonlinear circuits. This algorithm is based on interval analysis and linear programming techniques. The proposed algorithm is very efficient and can be easily implemented by using the free package GLPK (GNU Linear Programming Kit). By numerical examples, it is shown that the proposed algorithm could find all solutions of a system of 2 000 nonlinear circuit equations in practical computation time.

In this paper, we suggest a method of analyzing the post-wall waveguide (PWW) or the substrate integrated waveguide (SIW) by applying the analytical technique of the H-plane waveguide discontinuities based on the planar circuit approach. The analytical procedure consists of the derivation of the mode impedance matrices for regular-shaped circuits and the short-circuiting operation on fictitious ports arranged at the peripheries of the metallic posts. First, a straight section of the PWW is treated as an example and the analytical method for the calculation of the S-parameters is described in detail. Then the attenuation and phase constants of the PWW are computed with the aid of the Thru-Reflect Line (TRL) calibration technique. Next, the analytical method is applied to the design of two types of right-angled corners. The analysis and the design results are verified using an em-simulator (HFSS).

To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.

It has been known that testing of reversible circuits is relatively easier than conventional irreversible circuits in the sense that few test vectors are needed to cover all stuck-at faults. This paper shows, however, that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit using a polynomial time reduction from 3SAT to the problem. We also show non-trivial lower bounds for the size of a minimum complete test set.

Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

We fabricated both thin film transistors (TFTs) and diodes using zinc oxide (ZnO) and pentacene, and investigated their basic characteristics. We found that field-effect mobility is influenced by the interface state between the semiconductor and dielectric layers. Furthermore, the complementary metal oxide semiconductor (CMOS) inverter using a p-channel pentacene field-effect transistor (FET) and an n-channel ZnO FET showed a relatively high voltage gain (8-12) by optimizing the device structure. The hybrid complementary inverters described here are expected for application in flexible displays, radio frequency identification cards (RFID) tags, and others.

In this paper, active frequency selective surfaces (FSS) having a squared aperture with a metal plate loading are described. Active FSS elements using switched PIN diodes are discussed with an equivalent circuit model. A unit cell consists of a square aperture element with metal island loading and one PIN diode placed at the upper gap, considering the vertical polarization. The electromagnetic properties of the active FSS structure are changed by applying dc bias to the substrate, and they can be estimated by the equivalent circuit model of the FSS structure and PIN diode. This active FSS design enables transmission to be switched on or off at 2.3 GHz, providing high transmission when the diodes are in an off state and high isolation when the diodes are on. The equivalent circuit model in the structure is investigated by analyzing transmission and reflection spectra. Measurements on active FSS are compared with numerical calculations. The experimentally observed frequency responses are also scrutinized.

Current distribution on a 2-layer PCB with lumped circuits is estimated by measuring the near electric field. In this method, the current estimation model is made without considering the electrical parameters of lumped circuits. Experimental results are demonstrated and compared with the numerical results, confirming the validity of this method.

This paper represents a novel second harmonic power combining oscillator using mutually synchronized Gunn diodes embedded on slot line resonators. A both-sided MIC technology is adopted in the oscillator. The oscillator consists of Gunn diodes, slot line resonators and microstrip lines. By embedding Gunn diodes on the slot line resonators, the harmonic RF signal can be generated very easily. The microstrip lines are used for the power combining output circuit. This oscillator has advantages such as easy circuit design, simple circuit configuration and miniaturization of the circuit size. The second harmonic oscillator is designed and fabricated in K-Band. The output power is +5.75 dBm at the design frequency of 19.0 GHz (2f0) with the phase noise of -111.7 dBc/Hz at the offset frequency of 1 MHz. Excellent suppression of the undesired fundamental frequency signal (f0) of -39 dBc is achieved.

Compact and planar active integrated antenna arrays with a high power multi-stage amplifier were developed with effective heat sink mechanism. By attaching an aluminum plate to the backside of the creased amplifier circuit board, effective cooling can be achieved. The nonlinear behavior of the amplifier agrees well with the simulation based on the Angelov model. The high power amplifier circuit consisted of the three-stage amplifier and operated with an output power of 4 W per each element at 5.8 GHz. The 32-element active integrated antenna array stably operated with the output power of 120 W under the effective heat sink design. With a weight of 4 kg, the weight-to-output power ratio and the volume-to-output power ratio of the antenna array are 33.3 g/W and 54.5 cm3/W, respectively. Wireless power transmission was also successfully demonstrated.

This Letter employs transmission-line theory for the impedance-matching circuits for a single-chip power amplifier (PA) and verifies for 5 GHz-band wireless LAN (IEEE 802.11a) applications. The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverters. One of the advantages of the presented circuits is that it can save on-chip space occupied by the matching circuits compared to that using the spiral inductors, thus reducing the cost. The prototype chip, which consists of PA and matching circuits, is designed employing the presented theory and fabricated. A few of the measured results to verify the design theory are presented.

This paper introduces a theory for fast optimization of the circuit topology and parameters in sinusoidal oscillators. The theory starts from a system model composed of standard active and passive elements. We then include even the output load in the circuit, so that there is no longer any interaction with the outside of the system through the port. This model is thus called no-input-no-output (NINO) oscillator. The circuit is cut at an arbitrary branch, and is characterized in terms of the scalar impedance from the cut point. This is called active impedance because it is a function of not only the stimulating frequency but also the active device gain. The oscillation frequency and necessary device gain are estimated by solving impedance-domain Barkhausen equilibrium equations. This estimation works for the adjustment of circuit elements to meet the specified oscillation frequency. The estimation of necessary device gain enables us to maximize the oscillation amplitude, thanks to the inherent negative-slope nonlinearity of active devices. The active impedance is also used to derive the oscillation Q (quality) factor, which serves as a key criterion for sideband noise minimization i.e. frequency spectrum purification. As an alternative measure to active impedance, we also introduce branch admittance matrix determinant. This has the same numerical effect as the scalar impedance but can be used to formulate oscillator characteristics in a more elegant fashion, and provides a lucent picture of the physical behavior of each element in the circuit. Based on the proposed theory, we provide the tabled formulas of oscillation frequency, necessary device gain, active Q factor for a variety of typical Colpitts, Hartley, and cross-coupled twin-FET (field-effect transistor) oscillators.