IEICE TRANSACTIONS on Information
Design for Delay Fault Testability of 2-Rail Logic Circuits
Summary :
This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
- Publication
- IEICE TRANSACTIONS on Information Vol.E92-D No.2 pp.336-341
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E92.D.336
- Type of Manuscript
- LETTER
- Category
- Dependable Computing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, "Design for Delay Fault Testability of 2-Rail Logic Circuits" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 2, pp. 336-341, February 2009, doi: 10.1587/transinf.E92.D.336.
Abstract: This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.336/_p
Copy
@ARTICLE{e92-d_2_336,
author={Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Delay Fault Testability of 2-Rail Logic Circuits},
year={2009},
volume={E92-D},
number={2},
pages={336-341},
abstract={This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.},
keywords={},
doi={10.1587/transinf.E92.D.336},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Design for Delay Fault Testability of 2-Rail Logic Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 336
EP - 341
AU - Kentaroh KATOH
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transinf.E92.D.336
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2009
AB - This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
ER -
English
