This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.