Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths

Kentaroh KATOH; Kazuteru NAMBA; Hideo ITO

doi:10.1587/transinf.E92.D.433

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths

Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO

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This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.

Publication: IEICE TRANSACTIONS on Information Vol.E92-D No.3 pp.433-442

Publication Date: 2009/03/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E92.D.433

Type of Manuscript: PAPER

Category: Dependable Computing

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Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, "Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths" in IEICE TRANSACTIONS on Information, vol. E92-D, no. 3, pp. 433-442, March 2009, doi: 10.1587/transinf.E92.D.433.
Abstract: This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.433/_p

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@ARTICLE{e92-d_3_433,
author={Kentaroh KATOH, Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths},
year={2009},
volume={E92-D},
number={3},
pages={433-442},
abstract={This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.},
keywords={},
doi={10.1587/transinf.E92.D.433},
ISSN={1745-1361},
month={March},}

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TY - JOUR
TI - Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
T2 - IEICE TRANSACTIONS on Information
SP - 433
EP - 442
AU - Kentaroh KATOH
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transinf.E92.D.433
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2009
AB - This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.
ER -