As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.

A new acceleration scheme that decreases the number of required iterations in relaxation methodology is proposed. The proposed scheme uses dynamic error prediction of an improved approximation to the solution during an iterative computation. The proposed scheme's application to circuit simulations required an average of 67.3% fewer iterations compared to un-accelerated relaxation methods.

The authors present R2Power, an effective approach to the realizable reduction of RC networks with independent current sources. The proposed approach is based on the entrywise perturbation theory for diagonally dominant M-matrices. The accuracy of the node voltages of the reduced network, as compared to those of the original network, is maintained on the order of the entrywise perturbation performed during reduction. R2Power can be used to reduce the size of RC networks used to model the power networks of SoCs, for efficient IR-drop analysis. Experiments showed that R2Power reduced the size of industrial examples by more than 95%, with maximum relative node voltage errors of less than 0.012%.