New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects

Tae Il BAE; Jin Wook KIM; Young Hwan KIM

doi:10.1093/ietfec/e91-a.12.3488

New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects

Tae Il BAE, Jin Wook KIM, Young Hwan KIM

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As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3488-3496

Publication Date: 2008/12/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.12.3488

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Device and Circuit Modeling and Analysis

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Tae Il BAE, Jin Wook KIM, Young Hwan KIM, "New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 12, pp. 3488-3496, December 2008, doi: 10.1093/ietfec/e91-a.12.3488.
Abstract: As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3488/_p

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@ARTICLE{e91-a_12_3488,
author={Tae Il BAE, Jin Wook KIM, Young Hwan KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects},
year={2008},
volume={E91-A},
number={12},
pages={3488-3496},
abstract={As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3488},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3488
EP - 3496
AU - Tae Il BAE
AU - Jin Wook KIM
AU - Young Hwan KIM
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3488
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.
ER -