A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.

The problem of designing a robust adaptive control for nonlinear systems with uncertain time-varying parameters is addressed. The upper bound of uncertain parameters, considered even in control coefficients, are not required to be known. An adaptive tracking controller is presented and, using the Lyapunov theory, the closed-loop stability and tracking error convergence is shown. In order to improve the performance of the method, a robust mechanism is incorporated into the adaptive controller yielding a robust adaptive algorithm. The proposed controller guarantees the boundedness of all closed-loop signals and robust convergence of tracking error in spite of time-varying parameter uncertainties with unknown bounds. The parametric uncertain systems under consideration describes a wide class of nonlinear circuits and systems. As an application, a novel parametric model is derived for nonlinear Chua's circuit and then, the proposed method is used for its control. The effectiveness of the method is demonstrated by some simulation results.

An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.

In this research, the practical OTA-based inductors of all structures have been studied and their complete passive equivalent circuit models, where the effects of both parasitic elements and finite opened-loop bandwidth have been taken into account, also contain only the conventional standard linear elements i.e. the ordinary resistor, inductor and capacitor, without any infeasible high order element e.g. super inductor etc., have been proposed. The resulting models have been found to be excellently accurate, excellently straight forward, far superior to the previously proposed ones and completely realizable by the passive elements. Hence, the proposed passive equivalent circuit models have been found to be the convenience and versatile tools for the implementation of any analog and mixed signal processing circuits and systems.

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

We have developed a compact double-gate metal-oxide-semiconductor field-effect transistor model for circuit simulation considering the volume inversion effect by solving the Poisson equation explicitly. It is verified that applied voltage dependence of the calculated potential values both at the surface and at the center of the silicon layer reproduce 2 dimensional device simulation results for any device structure, confirming the validity of the model for device optimization.

The gas-puffer effect has important effects on the interruption capability of a molded case circuit breaker (MCCB). In this paper, on the basis of a simplified model of an arc chamber with a single break, the effect of back-volume of an arc-quenching chamber on arc behavior in an MCCB is investigated. Firstly, using a 2-D optical-fiber arc-motion measurement system, experiments are performed to study the effect of back-volume on the arc-motion and gas pressure in an arc-quenching chamber. We demonstrate that the lower back-volume of the arc-quenching chamber is, the higher the pressure and the better the arc motion will be. Then, corresponding to the above experiments, the gas pressure inside the arc-quenching chamber is calculated using the integral conservation equation. The simulation results are consistent with the experimental results.

This paper simulates the dynamic behavior of the operating mechanism of ACB, and analyzes factors influencing the mechanism's operating time. First, it builds a dynamic model for the mechanism with virtual prototype technology. Experiment validation is carried out to prove the correctness of the model. Based on this model, it puts emphasis on analyzing the influence of electro-dynamic repulsion force on the operating time of the mechanism. Simulation and experimental results show that after adding electric repulsion force to the model, the operating time is shortened about 1.1 ms. Besides the repulsion force, other influencing factors including the stiffness of opening spring, locations of every key axis, mass and centroidal coordinates of every mechanical part are analyzed as well. Finally, it makes an optimum design for the mechanism. After optimization, the velocity of operating mechanism is improved about 6.7%.

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Short-time withstand current is one of the crucial nominal parameters in air circuit breaker. A numerical method to evaluate the short-time withstand current is proposed. Cylindrical current carrying bridge is introduced to describe the contact spot between movable and fixed contacts. Taking into account the action of ferromagnetic splitter plates, the variation of the conductor properties with temperature and the variation of contact spot radius with the electro-dynamic repulsion force, a transient finite element calculation model is developed by coupling the electromagnetic field and thermal field. The loaded short circuit current is considered as the short-time withstand current once the highest temperature is near to the melting point of the contact material. It demonstrates that the method is useful to evaluate the performance of the air circuit breaker.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

A new type of algorithm for predicting the mechanical faults of a vacuum circuit breaker (VCB) based on an artificial neural network (ANN) is proposed in this paper. There are two types of mechanical faults in a VCB: operation mechanism faults and tripping circuit faults. An angle displacement sensor is used to measure the main axle angle displacement which reflects the displacement of the moving contact, to obtain the state of the operation mechanism in the VCB, while a Hall current sensor is used to measure the trip coil current, which reflects the operation state of the tripping circuit. Then an ANN prediction algorithm based on a sliding time window is proposed in this paper and successfully used to predict mechanical faults in a VCB. The research results in this paper provide a theoretical basis for the realization of online monitoring and fault diagnosis of a VCB.

VI time responses of a conventional electromagnetic relay during breaking contact operations were measured. In a conventional switching circuit, unstable contact resistance, irregular bouncing, and poor reproducibility were confirmed. Using a transient current switch circuit and two sharpened contact electrodes, bouncing during a breaking operation was suppressed, and unstable contact resistance changes and reproducibility of breaking operation were also improved.

On the basis of the RF characteristics of p-type diamond field-effect transistors (FETs) with hydrogen surface termination, we establish an equivalent circuit (EQC) model. From comparisons of three cases we reveal that to represent the device performance in the EQC, the source, gate, and drain resistance should be considered but that the gate-source and gate-drain resistance can be ignored. The features of diamond FETs are (1) a plateau of the gate capacitance in a certain gate voltage range. (2) maximum fT and fMAX cut-off frequencies near the threshold gate voltage, and (3) a high fMAX/fT ratio 3.8. We discuss these features in terms of the energy barrier between the gate metal and the two-dimensional hole channel and drift region below the gate.

This paper will review the development of SiC power devices especially SiC power junction field-effect transistors (JFETs). Rationale and different approaches to the development of SiC power JFETs will be presented, focusing on normally-OFF power JFETs that can provide the highly desired fail-save feature for reliable power switching applications. New results for the first demonstration of SiC Power ICs will be presented and the potential for distributed DC-DC power converters at frequencies higher than 35 MHz will be discussed.

The performance of recently developed Large Signal (LS) HBT model was evaluated with extensive LS measurements like Power spectrum, Load pull and Inter-modulation investigations. Proposed model has adopted temperature dependent leakage resistance and a simplified capacitance models. The model was implemented in ADS as SDD. Important feature of the model is that the main model parameters are taken directly from measurements in rather simple and understandable way. Results show good accuracy despite the simplicity of the model. To our knowledge the HBT model is one of a few HBT models which can handle high current & Power HBT devices, with significantly less model parameters with good accuracy.

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.

Open circuit voltage (OCV) of electrical devices is an issue in various fields, whose numerical evaluation needs careful treatment. The open-circuited structure is ill-conditioned because of the singular electric field at the corners, and the TEM component of the electric field has to be extracted before integrated to give the voltage in the direct method of obtaining the OCV. This paper introduces the indirect methods to calculate the OCV, the admittance matrix method and the Norton theorem method. Both methods are based on the short-circuited structure which is well-conditioned. The explicit expressions of the OCV are derived in terms of the admittance matrix elements in the admittance matrix method, and in terms of the short circuit current and the antenna impedance of the electrical device under consideration in the Norton theorem method. These two methods are equivalent in theory, but the admittance matrix method is suitable for the nearby transmitter cases while the Norton theorem method is suitable for the distant transmitter cases. Several examples are given to show the usefulness of the present theory.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.