An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.