A Single Input Change Test Pattern Generator for Sequential Circuits
Summary :
An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.8 pp.1365-1370
- Publication Date
- 2008/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.8.1365
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, "A Single Input Change Test Pattern Generator for Sequential Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 8, pp. 1365-1370, August 2008, doi: 10.1093/ietele/e91-c.8.1365.
Abstract: An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1365/_p
Copy
@ARTICLE{e91-c_8_1365,
author={Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Input Change Test Pattern Generator for Sequential Circuits},
year={2008},
volume={E91-C},
number={8},
pages={1365-1370},
abstract={An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.},
keywords={},
doi={10.1093/ietele/e91-c.8.1365},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A Single Input Change Test Pattern Generator for Sequential Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1365
EP - 1370
AU - Feng LIANG
AU - ShaoChong LEI
AU - ZhiBiao SHAO
PY - 2008
DO - 10.1093/ietele/e91-c.8.1365
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
ER -
English
