IEICE TRANSACTIONS on Electronics
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
Summary :
We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.8 pp.1338-1347
- Publication Date
- 2008/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.8.1338
- Type of Manuscript
- Special Section PAPER (Special Section on Microelectronic Test Structures (ICMTS2007))
- Category
Authors
Masako FUJII
Koji NII
Hiroshi MAKINO
Shigeki OHBAYASHI
Motoshige IGARASHI
Takeshi KAWAMURA
Miho YOKOTA
Nobuhiro TSUDA
Tomoaki YOSHIZAWA
Toshikazu TSUTSUI
Naohiko TAKESHITA
Naofumi MURATA
Tomohiro TANAKA
Takanari FUJIWARA
Kyoko ASAHINA
Masakazu OKADA
Kazuo TOMITA
Masahiko TAKEUCHI
Shigehisa YAMAMOTO
Hiromitsu SUGIMOTO
Hirofumi SHINOHARA
Keyword
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Masako FUJII, Koji NII, Hiroshi MAKINO, Shigeki OHBAYASHI, Motoshige IGARASHI, Takeshi KAWAMURA, Miho YOKOTA, Nobuhiro TSUDA, Tomoaki YOSHIZAWA, Toshikazu TSUTSUI, Naohiko TAKESHITA, Naofumi MURATA, Tomohiro TANAKA, Takanari FUJIWARA, Kyoko ASAHINA, Masakazu OKADA, Kazuo TOMITA, Masahiko TAKEUCHI, Shigehisa YAMAMOTO, Hiromitsu SUGIMOTO, Hirofumi SHINOHARA, "A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 8, pp. 1338-1347, August 2008, doi: 10.1093/ietele/e91-c.8.1338.
Abstract: We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1338/_p
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@ARTICLE{e91-c_8_1338,
author={Masako FUJII, Koji NII, Hiroshi MAKINO, Shigeki OHBAYASHI, Motoshige IGARASHI, Takeshi KAWAMURA, Miho YOKOTA, Nobuhiro TSUDA, Tomoaki YOSHIZAWA, Toshikazu TSUTSUI, Naohiko TAKESHITA, Naofumi MURATA, Tomohiro TANAKA, Takanari FUJIWARA, Kyoko ASAHINA, Masakazu OKADA, Kazuo TOMITA, Masahiko TAKEUCHI, Shigehisa YAMAMOTO, Hiromitsu SUGIMOTO, Hirofumi SHINOHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology},
year={2008},
volume={E91-C},
number={8},
pages={1338-1347},
abstract={We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.},
keywords={},
doi={10.1093/ietele/e91-c.8.1338},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1338
EP - 1347
AU - Masako FUJII
AU - Koji NII
AU - Hiroshi MAKINO
AU - Shigeki OHBAYASHI
AU - Motoshige IGARASHI
AU - Takeshi KAWAMURA
AU - Miho YOKOTA
AU - Nobuhiro TSUDA
AU - Tomoaki YOSHIZAWA
AU - Toshikazu TSUTSUI
AU - Naohiko TAKESHITA
AU - Naofumi MURATA
AU - Tomohiro TANAKA
AU - Takanari FUJIWARA
AU - Kyoko ASAHINA
AU - Masakazu OKADA
AU - Kazuo TOMITA
AU - Masahiko TAKEUCHI
AU - Shigehisa YAMAMOTO
AU - Hiromitsu SUGIMOTO
AU - Hirofumi SHINOHARA
PY - 2008
DO - 10.1093/ietele/e91-c.8.1338
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.
ER -
English
