A novel structure of bandpass filter using NRD guide E-plane resonators is proposed. The NRD guide E-plane resonator is constructed by inserting metal foils in the E-plane of NRD guide. Simulation, fabrication and handling of the filter are very easy because each resonator is separated by simple metal foils. Chebyshev response bandpass filters are designed based on the theory of direct-coupled resonator filters and fabricated at 60 GHz. Simulated and measured filter performances agreed well with the design specifications. Insertion losses of the fabricated filters were found to be around 0.3 dB for 3-pole filter and 0.5 dB for 5-pole bandpass filter, respectively.

This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

A unified representation for various kinds of speculations and global scheduling algorithms is presented. After introducing several types of local and global speculations, reviewing our conventional method called conditional vector-based list scheduling, and discussing some of its limitations, we introduce the unique notion of generalized condition vectors (GCVs), which can represent most varieties of speculations and multiple branches as a single vector. The unification of parallel branches and partially unresolved nested conditional branches is discussed. Then, a scheduling algorithm using GCVs is proposed. Experimental results show the effectiveness of the GCV-based scheduling method.

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.

Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

This paper outlines the method of constructing single-electron logic circuits based on the binary decision diagram (BDD), a graphical representation of digital functions. The circuit consists of many unit devices, BDD devices, cascaded to build the tree of a BDD graph. Each BDD device corresponds to a node of the BDD graph and operates as a two-way switch for the transport of a single electron. Any combinatorial logic can be implemented using BDD circuits. Several subsystems for a single-electron processor have been constructed using semiconductor nano-process technology.

This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

Recently, efficient algorithms have been proposed for finding all characteristic curves of one-port piecewise-linear (PWL) resistive circuits. Using these algorithms, a middle scale one-port circuit can be represented by a PWL resistor that is neither voltage nor current controlled. By modeling often used one-port subcircuits by such resistors (macromodels), large scale circuits can be analyzed efficiently. In this paper, an efficient method is proposed for finding DC operating points of nonlinear circuits containing such neither voltage nor current controlled resistors using the SPICE-oriented approach. The proposed method can be easily implemented on SPICE without programming.

Recently, an efficient homotopy method termed the variable gain Newton homotopy (VGNH) method has been proposed for finding DC operating points of nonlinear circuits. This method is not only very efficient but also globally convergent for any initial point. However, the programming of sophisticated homotopy methods is often difficult for non-experts or beginners. In this paper, we propose an effective method for implementing the VGNH method on SPICE. By this method, we can implement a "sophisticated VGNH method with various efficient techniques" "easily" "without programming," "although we do not know the homotopy method well."

In this paper, a high-speed logic circuitry using bootstrapped and low-temperature polysilicon (LTPS) technologies for TFT-LCD panels is proposed. The new circuitry realizes high-speed operation owing to the application of a logic-swing voltage that is wider than the power-supply voltage using bootstrapped technology. As a result, the new logic circuitry can be operated at an operational frequency around 3-10 times higher than that of the conventional circuitry under the conditions of a 0.5 pF load capacitor at the output of a noninverting buffer and +10 V power-supply voltages. The new circuit is named "BST-TFT logic circuitry."

The pseudo-transient method is discussed in this paper as one of practical methods to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. The mathematical description for this method is presented and an effective pseudo-transient algorithm utilizing compound pseudo-elements is proposed. Numerical examples are demonstrated to prove that our algorithm is able to avoid the oscillation problems effectively and also improve the simulation efficiency.

A linear CMOS transconductor is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting to avoid the body effect. To annihilate the non-linear voltage terms, the substrate-bias effect of MOS transistors is treated more accurately in our design. Consequently, the non-linearity of the large-signal transconductance is reduced. The fabricated circuit occupies an area of 245 µm176 µm ( ≈approx 0.043 mm2) and dissipates 0.87 mW from a 3.3 V supply. For an input of 1 Vp-p, the measured output total harmonic distortion is less than 1.2%. The transconductance varies by less than 0.5% in the input range.

In this paper the attention is focused on the numerical study of hyperchaotic 2D-scroll attractors via the Adomian decomposition method. The approach, which provides series solutions of the system equations, is first applied to weakly-coupled Chua's circuits with Hermite interpolating polynomials. Then the method is successfully utilized for achieving hyperchaos synchronization of two coupled Chua's circuits. The reported examples show that the approach presents two main features, i.e., the system nonlinearity is preserved and the chaotic solution is provided in a closed form.

To give comprehensive and consecutive understanding about load line regulation in the previous companion paper [1], more generalized expansion and theoretical derivation will be proposed in this paper. The paper provides an alternative current control approach to control the bias voltage compensation for full-color LED display based on the load-line approach. Modeling and formulation of the driver circuit system will be discussed in detail. Bias voltage compensation based on three load-lines regulation will keep the operating point fixed for the three color cells. Many properties can be observed based on the proposed model. Parasite effect such as the stray resistor and the stray capacitor will be considered in this paper. The associated standard RGB color testing for color cells and white color testing will be illustrated to verify the proposed compensation for the display driver circuit. The objectives of the luminance uniformity and the gray scale control can be achieved by using circuit approach. It is believed that this paper will be helpful to the driver circuit technology for the full-color LED display.

DC motors are indispensable to improve the automotive functions. Recently, 70-100 motors are installed on luxury cars and this number is increasing year by year. With the recent demand for improved fuel economy and better equipment layout, the improvement of the motor's efficiency and the minimization of the motor size are the key to enhancing the competitive edge of the products. Adopting the high-density coil is an effective method for that, but it is accompanied by the commutation inductance rise which causes the commutation arc increase. The increase of commutation arc decreases motor life, because it causes the rise of brush/commutator wear. This report describes an arc-reducing effect obtained when capacitors are built into a commutation circuit for the purpose of reducing arcing under high commutation inductance conditions. The results of an evaluation using a equivalent commutation circuit and carbon brush/carbon flat-commutator showed that although a commutation circuit with built-in capacitor generated the same arc energy as a commutation circuit without a capacitor above a certain value of residual current, it displayed an excellent arc-reducing effect below that value of residual current.

To one double-breaker model, experimental investigation on blow open force was carried out. It demonstrates that the ratio between the emerging blow open force and arc power FB/ui decreases with the arcing time, the contact gap has less effect on FB/ui, and the characteristics of the blow open force are similar when the peak value of the short circuit current is beyond 4 kA. Then, according to the experimental data and conclusions, considering the influence of blow open force, the interruption process of molded case circuit breakers (MCCBs) was investigated. It demonstrates the blow open force has significant influence on interruption process and the proposed method is effective to evaluate new design of MCCBs.