IEICE TRANSACTIONS on Electronics
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic
Summary :
A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1575-1580
- Publication Date
- 2006/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.11.1575
- Type of Manuscript
- Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
- Category
Authors
Keyword
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Naoya ONIZAWA, Takahiro HANYU, "Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 11, pp. 1575-1580, November 2006, doi: 10.1093/ietele/e89-c.11.1575.
Abstract: A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1575/_p
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@ARTICLE{e89-c_11_1575,
author={Naoya ONIZAWA, Takahiro HANYU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic},
year={2006},
volume={E89-C},
number={11},
pages={1575-1580},
abstract={A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.},
keywords={},
doi={10.1093/ietele/e89-c.11.1575},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1575
EP - 1580
AU - Naoya ONIZAWA
AU - Takahiro HANYU
PY - 2006
DO - 10.1093/ietele/e89-c.11.1575
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
ER -
English
