This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

Cryptosystems for smartcard are required to provide protection from Differential Power Analysis (DPA) attack. Self-timed circuit based cryptosystems demonstrate considerable resistance against DPA attack, but they take substantial circuit area. A novel approach offering up to 30% area reduction and maintaining DPA protection level close to DIMS scheme is proposed.

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm 910 µm area.