IEICE TRANSACTIONS on Information
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Summary :
This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.8 pp.1632-1644
- Publication Date
- 2013/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.1632
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Yoshiya KOMATSU
Tohoku University
Masanori HARIYAMA
Tohoku University
Michitaka KAMEYAMA
Tohoku University
Keyword
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Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, "Architecture of an Asynchronous FPGA for Handshake-Component-Based Design" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 8, pp. 1632-1644, August 2013, doi: 10.1587/transinf.E96.D.1632.
Abstract: This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1632/_p
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@ARTICLE{e96-d_8_1632,
author={Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={Architecture of an Asynchronous FPGA for Handshake-Component-Based Design},
year={2013},
volume={E96-D},
number={8},
pages={1632-1644},
abstract={This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.},
keywords={},
doi={10.1587/transinf.E96.D.1632},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
T2 - IEICE TRANSACTIONS on Information
SP - 1632
EP - 1644
AU - Yoshiya KOMATSU
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2013
DO - 10.1587/transinf.E96.D.1632
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2013
AB - This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.
ER -
English
