Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.
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Yoshinobu HIGAMI, Seiji KAJIHARA, Irith POMERANZ, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, "On Finding Don't Cares in Test Sequences for Sequential Circuits" in IEICE TRANSACTIONS on Information,
vol. E89-D, no. 11, pp. 2748-2755, November 2006, doi: 10.1093/ietisy/e89-d.11.2748.
Abstract: Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.11.2748/_p
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@ARTICLE{e89-d_11_2748,
author={Yoshinobu HIGAMI, Seiji KAJIHARA, Irith POMERANZ, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Information},
title={On Finding Don't Cares in Test Sequences for Sequential Circuits},
year={2006},
volume={E89-D},
number={11},
pages={2748-2755},
abstract={Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.},
keywords={},
doi={10.1093/ietisy/e89-d.11.2748},
ISSN={1745-1361},
month={November},}
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TY - JOUR
TI - On Finding Don't Cares in Test Sequences for Sequential Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 2748
EP - 2755
AU - Yoshinobu HIGAMI
AU - Seiji KAJIHARA
AU - Irith POMERANZ
AU - Shin-ya KOBAYASHI
AU - Yuzo TAKAMATSU
PY - 2006
DO - 10.1093/ietisy/e89-d.11.2748
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2006
AB - Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.
ER -