IEICE TRANSACTIONS on Electronics
Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise
Summary :
Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1559-1566
- Publication Date
- 2006/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.11.1559
- Type of Manuscript
- Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Mitsuya FUKAZAWA, Makoto NAGATA, "Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 11, pp. 1559-1566, November 2006, doi: 10.1093/ietele/e89-c.11.1559.
Abstract: Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1559/_p
Copy
@ARTICLE{e89-c_11_1559,
author={Mitsuya FUKAZAWA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise},
year={2006},
volume={E89-C},
number={11},
pages={1559-1566},
abstract={Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.},
keywords={},
doi={10.1093/ietele/e89-c.11.1559},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise
T2 - IEICE TRANSACTIONS on Electronics
SP - 1559
EP - 1566
AU - Mitsuya FUKAZAWA
AU - Makoto NAGATA
PY - 2006
DO - 10.1093/ietele/e89-c.11.1559
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.
ER -
English
