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[Author] Naoki KATO(15hit)

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  • Users' Preference Prediction of Real Estate Properties Based on Floor Plan Analysis

    Naoki KATO  Toshihiko YAMASAKI  Kiyoharu AIZAWA  Takemi OHAMA  

     
    PAPER-Artificial Intelligence, Data Mining

      Pubricized:
    2019/11/20
      Vol:
    E103-D No:2
      Page(s):
    398-405

    With the recent advances in e-commerce, it has become important to recommend not only mass-produced daily items, such as books, but also items that are not mass-produced. In this study, we present an algorithm for real estate recommendations. Automatic property recommendations are a highly difficult task because no identical properties exist in the world, occupied properties cannot be recommended, and users rent or buy properties only a few times in their lives. For the first step of property recommendation, we predict users' preferences for properties by combining content-based filtering and Multi-Layer Perceptron (MLP). In the MLP, we use not only attribute data of users and properties, but also deep features extracted from property floor plan images. As a result, we successfully predict users' preference with a Matthews Correlation Coefficient (MCC) of 0.166.

  • Inserting Points Uniformly at Every Instance

    Sachio TERAMOTO  Tetsuo ASANO  Naoki KATOH  Benjamin DOERR  

     
    INVITED PAPER

      Vol:
    E89-D No:8
      Page(s):
    2348-2356

    Arranging n points as uniformly as possible is a frequently occurring problem. It is equivalent to packing n equal and non-overlapping circles in a unit square. In this paper we generalize this problem in such a way that points are inserted one by one with uniformity preserved at every instance. Our criterion for uniformity is to minimize the gap ratio (which is the maximum gap over the minimum gap) at every point insertion. We present a linear time algorithm for finding an optimal n-point sequence with the maximum gap ratio bounded by in the 1-dimensional case. We describe how hard the same problem is for a point set in the plane and propose a local search heuristics for finding a good solution.

  • Characteristics of Arc-Reducing Effect by Capacitor in Commutation Circuit

    Ryoichi HONBO  Youichi MURAKAMI  Hiroyuki WAKABAYASHI  Shinji UEDA  Kenzo KIYOSE  Naoki KATO  

     
    PAPER-Arc Discharge & Related Phenomena

      Vol:
    E89-C No:8
      Page(s):
    1153-1159

    DC motors are indispensable to improve the automotive functions. Recently, 70-100 motors are installed on luxury cars and this number is increasing year by year. With the recent demand for improved fuel economy and better equipment layout, the improvement of the motor's efficiency and the minimization of the motor size are the key to enhancing the competitive edge of the products. Adopting the high-density coil is an effective method for that, but it is accompanied by the commutation inductance rise which causes the commutation arc increase. The increase of commutation arc decreases motor life, because it causes the rise of brush/commutator wear. This report describes an arc-reducing effect obtained when capacitors are built into a commutation circuit for the purpose of reducing arcing under high commutation inductance conditions. The results of an evaluation using a equivalent commutation circuit and carbon brush/carbon flat-commutator showed that although a commutation circuit with built-in capacitor generated the same arc energy as a commutation circuit without a capacitor above a certain value of residual current, it displayed an excellent arc-reducing effect below that value of residual current.

  • Online Vertex Exploration Problems in a Simple Polygon

    Yuya HIGASHIKAWA  Naoki KATOH  

     
    PAPER

      Vol:
    E96-D No:3
      Page(s):
    489-497

    This paper considers online vertex exploration problems in a simple polygon where starting from a point in the inside of a simple polygon, a searcher is required to explore a simple polygon to visit all its vertices and finally return to the initial position as quickly as possible. The information of the polygon is given online. As the exploration proceeds, the searcher gains more information of the polygon. We give a 1.219-competitive algorithm for this problem. We also study the case of a rectilinear simple polygon, and give a 1.167-competitive algorithm.

  • Bicriteria Network Optimization Problems

    Naoki KATOH  

     
    INVITED PAPER

      Vol:
    E75-A No:3
      Page(s):
    321-329

    This paper presents a survey on bicriteria network optimization problems. When there are two conflicting criteria that evaluate the solution, the bicriteria optimization is to find a solution for which these criteria are both acceptably satisfied. Standard approaches to these problems are to combine these two criteria into an aggregated single criterion. Among such problems, this paper first deals with the case in which the aggregated objective function, denoted h(f1(x), f2(x)), is convex in original two objectives f1(x) and f2(x), and, as its special case, it reviews a strongly polynomial algorithm for the bicriteria minimum-cost circulation problem. It then discusses the case in which h is concave and demonstrates that a parametric approach is effective for this case. Several interesting applications in network optimization that belong to this class are also introduced. Finally we deal with the minimum range problems which seek to find a solution such that weights of the components used in the solution are most uniform. We shall present efficient algorithms for solving these problems arised in network optimization.

  • Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS

    Naoki KATO  Yohei AKITA  Mitsuru HIRAKI  Takeo YAMASHITA  Teruhisa SHIMIZU  Fuyuhiko MAKI  Kazuo YANO  

     
    PAPER

      Vol:
    E83-C No:11
      Page(s):
    1747-1754

    Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.

  • Design Concept and Characteristics of a Power Supply for Optical Network Units in FTTH Systems

    Seiichi MUROYAMA  Mikio YAMASAKI  Kazuhiko TAKENO  Naoki KATO  Ichiro YAMADA  

     
    PAPER-Power Supply

      Vol:
    E81-B No:5
      Page(s):
    1087-1094

    This paper describes the design concept and characteristics of a power supply for optical network units in Fiber To The Home (FTTH) systems. Powering architectures of local powering, network powering and power hub powering are compared in terms of cost and maintainability. A local powering architecture is selected for an ONU power supply because it is the most cost-effective overall compared with the others. The local power supply is mainly composed of a rectifier, DC-DC converters, a ringer, and batteries. A battery deterioration test function is important for the local power supply because battery lifetime varies depending on ambient temperature, discharge history, and charging conditions, and it is shorter than other electrical components used in ONU. Supplying power using alternative batteries is also necessary because the capacity of batteries installed in the power supply is limited. These functions and electrical characteristics are checked using an experimental power supply with Ni-Cd batteries.

  • High Speed GaAs 8 b ALU

    Masayuki INO  Tohru TAKADA  Masao IDA  Naoki KATO  

     
    LETTER-Compound Semiconductor Devices

      Vol:
    E69-E No:4
      Page(s):
    302-304

    A high speed GaAs 8 b ALU has been developed for application to video data processing. The ALU was designed using LSCFL and fabricated with 0.5µm BP-SAINT FETs. Very high speed operation of 1.2 ns critical path delay time corresponding to 84 ps/gate was obtained.

  • An Efficient Algorithm for Evacuation Problem in Dynamic Network Flows with Uniform Arc Capacity

    Naoyuki KAMIYAMA  Naoki KATOH  Atsushi TAKIZAWA  

     
    INVITED PAPER

      Vol:
    E89-D No:8
      Page(s):
    2372-2379

    In this paper, we consider the quickest flow problem in a network which consists of a directed graph with capacities and transit times on its arcs. We present an O(n log n) time algorithm for the quickest flow problem in a network of grid structure with uniform arc capacity which has a single sink where n is the number of vertices in the network.

  • Lower Bounds for the Thickness and the Total Number of Edge Crossings of Euclidean Minimum Weight Laman Graphs and (2,2)-Tight Graphs Open Access

    Yuki KAWAKAMI  Shun TAKAHASHI  Kazuhisa SETO  Takashi HORIYAMA  Yuki KOBAYASHI  Yuya HIGASHIKAWA  Naoki KATOH  

     
    PAPER-Fundamentals of Information Systems

      Pubricized:
    2024/02/16
      Vol:
    E107-D No:6
      Page(s):
    732-740

    We explore the maximum total number of edge crossings and the maximum geometric thickness of the Euclidean minimum-weight (k, ℓ)-tight graph on a planar point set P. In this paper, we show that (10/7-ε)|P| and (11/6-ε)|P| are lower bounds for the maximum total number of edge crossings for any ε > 0 in cases (k,ℓ)=(2,3) and (2,2), respectively. We also show that the lower bound for the maximum geometric thickness is 3 for both cases. In the proofs, we apply the method of arranging isomorphic units regularly. While the method is developed for the proof in case (k,ℓ)=(2,3), it also works for different ℓ.

  • FOREWORD

    Naoki KATOH  

     
    FOREWORD

      Vol:
    E79-A No:4
      Page(s):
    427-427
  • Variance-Based k-Clustering Algorithms by Voronoi Diagrams and Randomization

    Mary INABA  Naoki KATOH  Hiroshi IMAI  

     
    PAPER-Algorithms

      Vol:
    E83-D No:6
      Page(s):
    1199-1206

    In this paper we consider the k-clustering problem for a set S of n points pi=(xi) in the d-dimensional space with variance-based errors as clustering criteria, motivated from the color quantization problem of computing a color lookup table for frame buffer display. As the inter-cluster criterion to minimize, the sum of intra-cluster errors over every cluster is used, and as the intra-cluster criterion of a cluster Sj, |Sj|α-1 Σpi Sj ||xi - - x (Sj)||2 is considered, where |||| is the L2 norm and - x (Sj) is the centroid of points in Sj, i. e. , (1/|Sj|)Σpi Sj xi. The cases of α=1,2 correspond to the sum of squared errors and the all-pairs sum of squared errors, respectively. The k-clustering problem under the criterion with α = 1,2 are treated in a unified manner by characterizing the optimum solution to the k-clustering problem by the ordinary Euclidean Voronoi diagram and the weighted Voronoi diagram with both multiplicative and additive weights. With this framework, the problem is related to the generalized primary shatter function for the Voronoi diagrams. The primary shatter function is shown to be O(nO(kd)), which implies that, for fixed k, this clustering problem can be solved in a polynomial time. For the problem with the most typical intra-cluster criterion of the sum of squared errors, we also present an efficient randomized algorithm which, roughly speaking, finds an ε-approximate 2-clustering in O(n(1/ε)d) time, which is quite practical and may be used to real large-scale problems such as the color quantization problem.

  • Ultra-High-Speed GaAs BFL Binary Frequency Divider

    Kazuo OSAFUNE  Kuniki OHWADA  Naoki KATO  

     
    PAPER-Integrated Circuits

      Vol:
    E69-E No:4
      Page(s):
    536-543

    Using buffered GaAs MESFET logic (BFL) circuits with source follower architecture, ultra-high-speed, master-slave, flip-flop circuits were designed and fabricated. Newly-developed buried p-layer SAINT-FETs with 0.5 µm gate length by electron-beam lithography were used in the frequency divider IC process. A maximum operating frequency of the binary frequency divider was 6.8 GHz with a power consumption of 350 mW. Using dislocation free wafers, a 100% fabrication yield for more than 3.3 GHz operation was attained from four wafers; all frequency divider chips from one wafer operated at more than 5.1 GHz. Using the Advanced SAINT process, a maximum operating frequency of 9.2 GHz with a power consumption of 290 mW was also obtained based on the same circuit design.

  • Finding an Optimal Region in One- and Two-Dimensional Arrays

    Naoki KATOH  

     
    INVITED SURVEY PAPER-Algorithms for Geometric Problems

      Vol:
    E83-D No:3
      Page(s):
    438-446

    Given N real weights w1, w2, . . . , wN stored in one-dimensional array, we consider the problem for finding an optimal interval I [1, N] under certain criteria. We shall review efficient algorithms developed for solving such problems under several optimality criteria. This problem can be naturally extended to two-dimensional case. Namely, given a NN two-dimensional array of N2 reals, the problem seeks to find a subregion of the array (e. g. , rectangular subarray R) that optimizes a certain objective function. We shall also review several algorithms for such problems. We shall also mention applications of these problems to region segmentation in image processing and to data mining.

  • Finding a Triangular Mesh with a Constant Number of Different Edge Lengths

    Shin-ichi TANIGAWA  Naoki KATOH  

     
    INVITED PAPER

      Vol:
    E89-D No:8
      Page(s):
    2364-2371

    We consider the problem of triangulating an x-monotone polygon with a small number of different edge lengths using Steiner points. Given a parameter α, where 0<α<1, we shall present an algorithm for finding an almost uniform triangular mesh with 3π/8α2+o(1/α2) different edge lengths such that every edge length is between l and (2+α)l. Experiments demonstrate the effectiveness of this algorithm.