We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

This paper describes a metasurface designed utilizing either a Frequency Selective Surface (FSS) that has band-pass characteristics or one with band-rejection filtering characteristics in order to clarify the relationship between the filtering characteristics of the FSS and the Perfect Magnetic Conductor (PMC) characteristics of the metasurface. The effects of the filtering characteristics of the FSS on the PMC characteristics of the metasurface are described. Calculation results confirm that a low profile metasurface can be achieved using these FSSs. In addition, the effects of the size of the metasurface on the PMC characteristics of the surface are shown.

With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.

We explore the maximum total number of edge crossings and the maximum geometric thickness of the Euclidean minimum-weight (k, ℓ)-tight graph on a planar point set P. In this paper, we show that (10/7－ε)|P| and (11/6－ε)|P| are lower bounds for the maximum total number of edge crossings for any ε ＞ 0 in cases (k,ℓ)=(2,3) and (2,2), respectively. We also show that the lower bound for the maximum geometric thickness is 3 for both cases. In the proofs, we apply the method of arranging isomorphic units regularly. While the method is developed for the proof in case (k,ℓ)=(2,3), it also works for different ℓ.