Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation

Daisuke NOTSU; Naoya IKECHI; Yasuyuki AOKI; Nobuyuki KAWAKAMI; Kentaro SHIBAHARA

Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation

Daisuke NOTSU, Naoya IKECHI, Yasuyuki AOKI, Nobuyuki KAWAKAMI, Kentaro SHIBAHARA

Full Text Views

0

Cite this

Summary :

We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.5 pp.1119-1124

Publication Date: 2002/05/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)

Category

Cite this

Copy

Daisuke NOTSU, Naoya IKECHI, Yasuyuki AOKI, Nobuyuki KAWAKAMI, Kentaro SHIBAHARA, "Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 5, pp. 1119-1124, May 2002, doi: .
Abstract: We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1119/_p

Copy

@ARTICLE{e85-c_5_1119,
author={Daisuke NOTSU, Naoya IKECHI, Yasuyuki AOKI, Nobuyuki KAWAKAMI, Kentaro SHIBAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation},
year={2002},
volume={E85-C},
number={5},
pages={1119-1124},
abstract={We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1119
EP - 1124
AU - Daisuke NOTSU
AU - Naoya IKECHI
AU - Yasuyuki AOKI
AU - Nobuyuki KAWAKAMI
AU - Kentaro SHIBAHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.
ER -