We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

Breakdown fields and the charges to breakdown (QBD) of oxides increased after UV/Cl2 pre-oxidation cleaning. This is due to decreased residual metal contaminants on silicon surfaces in the bottom of the LOCOS region after wet cleaning. Treatment in NH4OH, H2O2 and H2O prior to UV/Cl2 cleaning suppressed increases in surface roughness and kept leakage currents through the oxides after UV/Cl2 cleaning as low as those after wet cleaning alone. The large junction leakage currents--caused by metal contaminants introduced during dry etching--decreased after UV/Cl2 cleaning which removes the contaminated layer.