We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100 nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900 which is lower than conventional 1000. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75 nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

Anomalous leakage current which flows between source and drain in thin film SOI MOSFET's is investigated. It is confirmed that the leakage current is caused by enhanced diffusion of the source/drain dopants along the LOCOS-induced crystal defects. Stress analysis by 2D simulation reveals that thinning a buried-oxide effectively suppresses deformation of an SOI film associated with over-oxidation during LOCOS. It is experimentally confirmed that using a SIMOX substrate which has a thinner buried-oxide causes no noticeable deformation of the SOI film nor anomalous leakage current.

Plasma damage to gate oxide is studied using the test structures with various length antennas. It is shown that the plasma damage to gate oxide can be monitored quantitatively by measuring charge to breakdown (QBD). From the QBD measurements, it is confirmed that the degradation occurs in the duration of over-etching but not in the duration of main etching. The breakdown spots in gate oxide are detected by a photon emission method. The breakdown are caused by plasma damage at the LOCOS edge. A LOCOS structure plays an important role for the degradation by the plasma damage.

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

A new channel stop design for submicton local oxidation of silicon (LOCOS) isolation was presented. The n-channel stop was designed with boron implanation after forming LOCOS, while the p-channel stop was constructed with high energy phosphorus or arsenic implantation before or after forming LOCOS. These optimized channel stop designs can extend an isolation spacing to the submicron region without a decrease in junction breakdown voltage and an increase in junction leakage current. Narrow channel effects were found to be effectively suppressed by optimum channel stop design issues.