The high speed and low power GaAs LSI is developed for application to a Giga bit rate digital data switching system using Low Power Source Coupled FET Logic. This LSI has functions of multiplexing, demultiplexing, frame pulse generation and three-stage counting. Eight and four bits operations over 1.3 Gbit/s data rate with less than 0.75 W power dissipation are achieved.

A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.

This paper reports a high-speed time division switching system using GaAs ICs. It also describes high-speed switching technologies including the fabrication of a 4-channel time division switch, a multi/ demultiplexer and peripheral circuit ICs, each having more than a 2 Gb/s throughput capability. In addition, such key factors as synchronous LSI operation, optimum circuit board designing and LSI packaging are presented. Finally it reports a great success in High Definition TV (HDTV) time division switching operation.

A high speed GaAs 8 b ALU has been developed for application to video data processing. The ALU was designed using LSCFL and fabricated with 0.5µm BP-SAINT FETs. Very high speed operation of 1.2 ns critical path delay time corresponding to 84 ps/gate was obtained.