This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

We have developed a design technique for static logic circuits. Using this technique, we designed 1/2 divider-type 1:4 demultiplexer (DEMUX) and 2:1 selector-type 4:1 multiplexer (MUX) circuits, each of which is a key component in high-speed data multiplexing and demultiplexing. These circuits consist of double rail flip-flops (DR F/F). These flip-flops have a smaller mean internal capacitance than single rail flip-flops, making them suitable for high-speed operation. The DR F/F has a symmetric structure, so the double rail toggle flip-flop can put out an exactly balanced CK/CKN signal, which boosts the speed of the data flip-flops. The double rail structure enables 30% faster operation but consumes only 17% more power (per GHz) than a single rail circuit. In addition, our 0.25-µm process technology provides a 70% higher frequency operation than 0.5-µm process technology. At the supply voltage of 2.2 V, the DEMUX circuit and the MUX circuit operate at 4.55 GHz and 2.98 GHz, respectively. In addition, the 0.25-µm DEMUX circuit and the MUX circuit respectively consume 6.0 mW/GHz and 13.7 mW/GHz (＠1.3 V), which are only 12% of the power consumed by 3.3-V 0.5-µm circuits. Because of its high-speed and low-power characteristics, our design technique will greatly contribute to the progress of large-scale high-speed telecommunication systems.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.

The operating life for a newly developed millimeter-wave silicon DDR IMPATT diode, which is hermetically sealed in a mechanically rugged miniature ceramic package with a diamond heat sink, is evaluated by accelerated life tests consisting of high-temperature storage and high-temperature DC operation. A mean time to failure (MTTF) value of approximately 2.6105 h (3800 FIT) is predicted at a junction temperature of 235, where the diode is capable of delivering an output power of 100 to 150 mW at 80 CHz band. The predominant failure mode is a junction short caused by gold diffusion into the silicon layer. An rf operating life test is also conducted. There has been no failure for 12,000 h.

Various high-performance SOI CMOS circuits were fabricated using fully-depleted 0.25-µm gate MOSFETs on a low-dose SIMOX substrate. 2.4-Gbps operations were achieved for I/O and speed conversion circuits which are key elements in a multimedia communication LSI. LVTTL-compatible gate array LSI was developed with an ESD protection circuit which is the first one to meer the MIL standard. A 120-kG test LSI was fabricated on the gate array, and the LSI performances using three kind of technologies; 0.25-µm bulk and SIMOX and 0.5-µm bulk; were compared. A 0.25-µm SIMOX LSI was 10% faster with 35% less power dissipation compared with a 0.25-µm bulk LSI. The 0.25-µm SIMOX LSI can operate at a VDD of 1.2 V to attain the same speed as the 0.5-µm bulk LSI operating at 3.3 V, and this results in 1/40 power reduction. For the high-speed communication use, an ATM-switch LSI with 220-kG and a 110-kb memory was fabricated. A high-performance of 2.5-Gbps interface speed and 312-Mbps internal speed were achieved using 0.25-µm CMOS/SIMOX. This ATM-switch LSI has the greatest bandwidth of 40-Gbps ever reported using a one-chip ATM-switch LSI.

A high speed GaAs 8 b ALU has been developed for application to video data processing. The ALU was designed using LSCFL and fabricated with 0.5µm BP-SAINT FETs. Very high speed operation of 1.2 ns critical path delay time corresponding to 84 ps/gate was obtained.