IEICE TRANSACTIONS on transactions
Level Shift Circuits for GaAs Low Power Source Coupled FET Logic
Summary :
A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E70-E No.4 pp.224-226
- Publication Date
- 1987/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue: Papers from 1987 National Convention IEICE)
- Category
- Semiconductor Devices and Integrated Circuits
Authors
Keyword
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Masanobu OHHATA, Tohru TAKADA, Masayuki INO, Masao IDA, "Level Shift Circuits for GaAs Low Power Source Coupled FET Logic" in IEICE TRANSACTIONS on transactions,
vol. E70-E, no. 4, pp. 224-226, April 1987, doi: .
Abstract: A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e70-e_4_224/_p
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@ARTICLE{e70-e_4_224,
author={Masanobu OHHATA, Tohru TAKADA, Masayuki INO, Masao IDA, },
journal={IEICE TRANSACTIONS on transactions},
title={Level Shift Circuits for GaAs Low Power Source Coupled FET Logic},
year={1987},
volume={E70-E},
number={4},
pages={224-226},
abstract={A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Level Shift Circuits for GaAs Low Power Source Coupled FET Logic
T2 - IEICE TRANSACTIONS on transactions
SP - 224
EP - 226
AU - Masanobu OHHATA
AU - Tohru TAKADA
AU - Masayuki INO
AU - Masao IDA
PY - 1987
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E70-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1987
AB - A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.
ER -
English
