This paper describes a new automated approach to generating the patterns of CMOS leaf cells from transistor-level connectivity data. This method can generate CMOS leaf cells that are configurable to a macro cell satisfying user-specified constraints. The user-specified constraints include the aspect ratio and port positions of the macro cell. We propose a top-down method for converting the macro cell level constratints to leaf cell level ones. Using this method, a variety of customized macro cells can be designed in a short turn-around time. The method consists of four processes--diffusion sharing, initial placement, placement improvement and routing--which culminate in the automatic generation of symbolic representations. Using a compactor, those symbolic representations can be converted to physical patterns which are gathered into a macro cell by a macro generator. We define various objective functions to improve unit pair placement. We also introduce five ways to optimize leaf cell area: 1) multi-row division, 2) gate division 3) rotation, 4) power line and diffusion overlapping and 5) reconstruction of hierarchical structure. The proposed approach has been applied to various kinds of CMOS leaf cells. Experimental results show that the generated cells have almost the same areas as those generated by conventional bottom-up approaches in leaf and macro cell layouts. This approach offers a further advantage in that the various-sized macro cells required by layout disigners can also be generated.

This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.