A 40-Gb/s 8<cd0215f.gif>8 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX

Yusuke OHTOMO; Sadayuki YASUDA; Masafumi NOGAWA; Jun-ichi INOUE; Kimihiro YAMAKOSHI; Hirotoshi SAWADA; Masayuki INO; Shigeki HINO; Yasuhiro SATO; Yuichiro TAKEI; Takumi WATANABE; Ken TAKEYA

A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX

Yusuke OHTOMO, Sadayuki YASUDA, Masafumi NOGAWA, Jun-ichi INOUE, Kimihiro YAMAKOSHI, Hirotoshi SAWADA, Masayuki INO, Shigeki HINO, Yasuhiro SATO, Yuichiro TAKEI, Takumi WATANABE, Ken TAKEYA

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The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.5 pp.737-745

Publication Date: 1998/05/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)

Category: Network

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Yusuke OHTOMO, Sadayuki YASUDA, Masafumi NOGAWA, Jun-ichi INOUE, Kimihiro YAMAKOSHI, Hirotoshi SAWADA, Masayuki INO, Shigeki HINO, Yasuhiro SATO, Yuichiro TAKEI, Takumi WATANABE, Ken TAKEYA, "A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 5, pp. 737-745, May 1998, doi: .
Abstract: The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_5_737/_p

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@ARTICLE{e81-c_5_737,
author={Yusuke OHTOMO, Sadayuki YASUDA, Masafumi NOGAWA, Jun-ichi INOUE, Kimihiro YAMAKOSHI, Hirotoshi SAWADA, Masayuki INO, Shigeki HINO, Yasuhiro SATO, Yuichiro TAKEI, Takumi WATANABE, Ken TAKEYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX},
year={1998},
volume={E81-C},
number={5},
pages={737-745},
abstract={The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX
T2 - IEICE TRANSACTIONS on Electronics
SP - 737
EP - 745
AU - Yusuke OHTOMO
AU - Sadayuki YASUDA
AU - Masafumi NOGAWA
AU - Jun-ichi INOUE
AU - Kimihiro YAMAKOSHI
AU - Hirotoshi SAWADA
AU - Masayuki INO
AU - Shigeki HINO
AU - Yasuhiro SATO
AU - Yuichiro TAKEI
AU - Takumi WATANABE
AU - Ken TAKEYA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1998
AB - The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.
ER -