In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.