This paper proposes a sub-signal channel modulation scheme for hitless redundancy switching systems that offers highly confidential communications. A hitless redundancy switching system prevents frame loss by using multiple routes to forward the same frame. Although most studies on redundancy switching systems deal with frame duplication, elimination, and selection of redundant paths for the main signal, we focus on the transmission of the sub-signal channel. We introduce mathematical expressions to model the transmission rate and bit error rate of the sub-signal channel. To evaluate the validity of the models, we conduct numerical simulations to calculate the sub-signal transmission rate, main-signal transmission rate, and bit error rate of the sub-signal channel at physical transmission rates of 100Mb/s, 1Gb/s, and 10Gb/s. We discuss how to design sub-signal channel modulation on the basis of the evaluation results. We further discuss applications of sub-signal modulation in terms of network size and jitter.

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

We developed a compact, 16-channel integrated optical subscriber module for one-fiber bi-directional optical access systems. They can support more subscribers in a limited mounting space. For ultimate compactness, we created 8-channel integrated super-compact optical modules, 4-channel integrated limiting amplifiers, and 4-channel integrated LD drivers for Fast Ethernet. We introduce a new simulation method to analyze the electrical crosstalk that degrades sensitivity of the optical module. A new IC architecture is applied to reduce electrical crosstalk. We manufactured the optical subscriber module with these optical modules and ICs. Experiments confirm that the module offers a sensitivity of -27.3 dBm under 16-channel 125 Mbit/s simultaneous operation.