A demonstration of power enhancement by nonlinear oscillation in a millimeter-sized electrostatic vibrational energy harvester for the future Internet of Things is presented. To enable nonlinearity in microelectromechanical system (MEMS) devices, we selected a gold spring as a component of the MEMS structure for its lower Young's modulus than conventional materials, a ductile characteristic, and an electrical conductivity. The mechanical characteristics of the fabricated MEMS device related to the nonlinear phenomenon were examined. The charging characteristics of an ethylene tetrafluoroethylene copolymer (ETFE) electret film for electrostatic induction were also evaluated. Nonlinear oscillation for the millimeter-sized energy harvester with the ETFE electret was confirmed experimentally by applying external vibration. The oscillation resulted in a bandwidth two times broader than that by linear oscillation. The normalized harvester effectiveness of the nonlinear oscillation was 5.1 times higher than that of the linear one.

The current distribution along a square spiral arm is determined by using Mei's integral equation. The data concerning radiation pattern, power gain, axial ratio and input impedance are presented with good agreement between theoretical and experimental results over a frequency range of 3 to 7 GHz. It is revealed that similar decay in the current distribution, which is necessary to keep wide-band characteristics of the radiation, is obtained in spite of the change of frequency. The data show that the input impedance is nearly a pure resistance, and that, when the radiation pattern in the spiral plane becomes almost omnidirectional, phase of the radiation field varies linearly with the change of the azimuth.

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.

As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.