An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System

Hiroaki KATSURAI; Hideki KAMITSUNA; Hiroshi KOIZUMI; Jun TERADA; Yusuke OHTOMO; Tsugumichi SHIBATA

doi:10.1587/transele.E94.C.582

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System

Hiroaki KATSURAI, Hideki KAMITSUNA, Hiroshi KOIZUMI, Jun TERADA, Yusuke OHTOMO, Tsugumichi SHIBATA

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As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10^-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.582-588

Publication Date: 2011/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.582

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

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Hiroaki KATSURAI, Hideki KAMITSUNA, Hiroshi KOIZUMI, Jun TERADA, Yusuke OHTOMO, Tsugumichi SHIBATA, "An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 582-588, April 2011, doi: 10.1587/transele.E94.C.582.
Abstract: As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10^-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.582/_p

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@ARTICLE{e94-c_4_582,
author={Hiroaki KATSURAI, Hideki KAMITSUNA, Hiroshi KOIZUMI, Jun TERADA, Yusuke OHTOMO, Tsugumichi SHIBATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System},
year={2011},
volume={E94-C},
number={4},
pages={582-588},
abstract={As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10^-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.},
keywords={},
doi={10.1587/transele.E94.C.582},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System
T2 - IEICE TRANSACTIONS on Electronics
SP - 582
EP - 588
AU - Hiroaki KATSURAI
AU - Hideki KAMITSUNA
AU - Hiroshi KOIZUMI
AU - Jun TERADA
AU - Yusuke OHTOMO
AU - Tsugumichi SHIBATA
PY - 2011
DO - 10.1587/transele.E94.C.582
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10^-12) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.
ER -