Ultra-High-Speed GaAs BFL Binary Frequency Divider

Kazuo OSAFUNE; Kuniki OHWADA; Naoki KATO

Ultra-High-Speed GaAs BFL Binary Frequency Divider

Kazuo OSAFUNE, Kuniki OHWADA, Naoki KATO

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Using buffered GaAs MESFET logic (BFL) circuits with source follower architecture, ultra-high-speed, master-slave, flip-flop circuits were designed and fabricated. Newly-developed buried p-layer SAINT-FETs with 0.5 µm gate length by electron-beam lithography were used in the frequency divider IC process. A maximum operating frequency of the binary frequency divider was 6.8 GHz with a power consumption of 350 mW. Using dislocation free wafers, a 100% fabrication yield for more than 3.3 GHz operation was attained from four wafers; all frequency divider chips from one wafer operated at more than 5.1 GHz. Using the Advanced SAINT process, a maximum operating frequency of 9.2 GHz with a power consumption of 290 mW was also obtained based on the same circuit design.

Publication: IEICE TRANSACTIONS on transactions Vol.E69-E No.4 pp.536-543

Publication Date: 1986/04/25

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Type of Manuscript: PAPER

Category: Integrated Circuits

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Kazuo OSAFUNE
Kuniki OHWADA
Naoki KATO

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Kazuo OSAFUNE, Kuniki OHWADA, Naoki KATO, "Ultra-High-Speed GaAs BFL Binary Frequency Divider" in IEICE TRANSACTIONS on transactions, vol. E69-E, no. 4, pp. 536-543, April 1986, doi: .
Abstract: Using buffered GaAs MESFET logic (BFL) circuits with source follower architecture, ultra-high-speed, master-slave, flip-flop circuits were designed and fabricated. Newly-developed buried p-layer SAINT-FETs with 0.5 µm gate length by electron-beam lithography were used in the frequency divider IC process. A maximum operating frequency of the binary frequency divider was 6.8 GHz with a power consumption of 350 mW. Using dislocation free wafers, a 100% fabrication yield for more than 3.3 GHz operation was attained from four wafers; all frequency divider chips from one wafer operated at more than 5.1 GHz. Using the Advanced SAINT process, a maximum operating frequency of 9.2 GHz with a power consumption of 290 mW was also obtained based on the same circuit design.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e69-e_4_536/_p

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@ARTICLE{e69-e_4_536,
author={Kazuo OSAFUNE, Kuniki OHWADA, Naoki KATO, },
journal={IEICE TRANSACTIONS on transactions},
title={Ultra-High-Speed GaAs BFL Binary Frequency Divider},
year={1986},
volume={E69-E},
number={4},
pages={536-543},
abstract={Using buffered GaAs MESFET logic (BFL) circuits with source follower architecture, ultra-high-speed, master-slave, flip-flop circuits were designed and fabricated. Newly-developed buried p-layer SAINT-FETs with 0.5 µm gate length by electron-beam lithography were used in the frequency divider IC process. A maximum operating frequency of the binary frequency divider was 6.8 GHz with a power consumption of 350 mW. Using dislocation free wafers, a 100% fabrication yield for more than 3.3 GHz operation was attained from four wafers; all frequency divider chips from one wafer operated at more than 5.1 GHz. Using the Advanced SAINT process, a maximum operating frequency of 9.2 GHz with a power consumption of 290 mW was also obtained based on the same circuit design.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Ultra-High-Speed GaAs BFL Binary Frequency Divider
T2 - IEICE TRANSACTIONS on transactions
SP - 536
EP - 543
AU - Kazuo OSAFUNE
AU - Kuniki OHWADA
AU - Naoki KATO
PY - 1986
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E69-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1986
AB - Using buffered GaAs MESFET logic (BFL) circuits with source follower architecture, ultra-high-speed, master-slave, flip-flop circuits were designed and fabricated. Newly-developed buried p-layer SAINT-FETs with 0.5 µm gate length by electron-beam lithography were used in the frequency divider IC process. A maximum operating frequency of the binary frequency divider was 6.8 GHz with a power consumption of 350 mW. Using dislocation free wafers, a 100% fabrication yield for more than 3.3 GHz operation was attained from four wafers; all frequency divider chips from one wafer operated at more than 5.1 GHz. Using the Advanced SAINT process, a maximum operating frequency of 9.2 GHz with a power consumption of 290 mW was also obtained based on the same circuit design.
ER -