A network for the detection of an approaching object with simple-shape recognition is proposed based on lower animal vision. The locust can detect an approaching object through a simple process in the descending contralateral movement detector (DCMD) in the locust brain, by which the approach velocity and direction of the object is determined. The frog can recognize simple shapes through a simple process in the tectum and thalamus in the frog brain. The proposed network is constructed of simple analog complementary metal oxide semiconductor (CMOS) circuits. The integrated circuit of the proposed network is fabricated with the 1.2 µm CMOS process. Measured results for the proposed circuit indicate that the approach velocity and direction of an object can be detected by the output current of the analog circuit based on the DCMD response. The shape of moving objects having simple shapes, such as circles, squares, triangles and rectangles, was recognized using the proposed frog-visual-system-based circuit.

A two-dimensional network for motion detection constructed of simple analog circuits was proposed and designed based on the frog visual system. In the frog visual system, the two-dimensional motion of a moving object can be detected by performing simple information processing in the tectum and thalamus of the frog brain. The measured results of the test chip fabricated by a 1.2 µm complementary metal oxide semiconductor (CMOS) process confirmed the correct operation of the basic circuits in the network. The results obtained with the simulation program with integrated circuit emphasis (SPICE) showed that the proposed network can detect the motion direction and velocity of a moving object. Thus, a chip for two-dimensional motion detection was realized using the proposed network.

The performance of parallel computing applications is highly dependent on the efficiency of the underlying communication operations. While often characterized as dynamic, these communication operations frequently exhibit spatial and temporal locality as well as regularity in structure. These characteristics can be exploited to improve communication performance if the correct prediction model is selected to a suitable communication topology. In this paper we describe an entropy based methodology for quantifying and evaluating the success of different prediction models on actual workloads drawn from representative parallel benchmarks. We evaluate two different prediction criteria and combinations thereof: (1) Messages are partitioned by source node. (2) Use of a first order context model. We also describe the threshold for predication designed to largely avoid incorrect predication overheads. Our results show for simple predication models, even on highly dynamic benchmark applications, predictability can be improved by several orders of magnitude. In fact, using simple prediction techniques, over 75% of the communication volume is accurately predictable.

This paper proposes a new approach for analog portion testing, which can meet requirements for high-speed and high-accuracy testing simultaneously with reasonable cost. The key concept of the new method is cooperation of an LSI tester and some circuitry built in a target SoC device. We will explain the operation principle of the proposed method. The proposed method can be one of the methods to overcome today's expensive production test of analog portion on SoC (System on Chip) devices which heavily depends on LSI tester capability and will become harder in near future.

In this letter, my proposals for a Floating node voltage-controlled Variable Resistor circuit (FVR) are based upon its advantages as linear and compact. The performance of the proposed circuit was confirmed by PSpice simulation. The simulation results are reported in this letter.

A coplanar type lumped-element 6-pole microwave Chebyshev bandpass filter (BPF) of center frequency (f0) 2.0 GHz and fractional bandwidth (FBW) 1.0 % was designed. For the design method, theory of direct coupled resonator filters using K-inverters was employed. Coplanar type lumped-element BPFs are composed of a meander-line L and interdigital C elements. The frequency response was simulated and analyzed using an electromagnetic field simulator (Sonnet-EM). Further, the changes in f0 and FBW of the BPF were also realized by the mechanical tuning method.

We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 µm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.

For emission from a printed circuit board (PCB) by the common-mode current, the suppression method based on the image theory by placing a conducting plate under the PCB is presented. In order to evaluate the suppression effect by this method the radiation power from the PCB is calculated by using FDTD method. The numerical results show that placing the conducting plate suppresses the emission by the common-mode current. Especially, using the conducting plate bent the sides, it is possible to suppress the emission by the small conducting plate. Further, the experimental results of a radiation power and a maximum electric field intensity show the validity of the numerical results.

This paper presents an improved gate drive circuit for high power GTO thyristors. The energy-storage/transfer characteristics of an air-core reactor and the fast switching characteristics of FET are employed to make a high gate current of sharp pulse form. The power loss in the gate drive circuit is reduced by using the low resistance and the hysteresis comparator to detect and control the steady on-gate current. The proposed gate drive circuit is analyzed and its usefulness is confirmed by experiments.

Techniques of near-field magnetic measurement and their applications to EMC of digital equipment are described. Magnetic-field measurement near PCB or LSI is the mostly used technique to specify the source. This paper treats an example of board analysis by near-field magnetic measurement, the sensing mechanism and the structure of a loop probe, and a recent progress of this method and application. To establish appropriate design direction in high-speed and high-density packaging of electronic equipment, electromagnetic behavior in chip and package should be clarified. Expectation of development for measuring minute area is more and more increasing.

To clarify the correspondence between Shielding Effectiveness (SE) of shielding materials and their physical property, we propose an equivalent circuit for a shielding effectiveness test apparatus using a dual TEM cell, and show its validity. By considering the structure of dual TEM cell that consists of a pair of cells coupled via an aperture in their common wall, we defined the capacitance C and mutual inductance M, that respectively express the electric coupling and magnetic coupling between two center conductors. By the measurement of unloaded S-parameter, we determined the values of C and M for a dual TEM cell in hand. Next, the shielding material was approximated by the apparent sheet resistivity Rs, and was used in the equivalent circuit of loaded aperture. As a result, the coupling level calculated from the equivalent circuit agreed well with the measured data in frequencies below 300 MHz.

Pattern extraction is an indispensable step in bare printed circuit board (PCB) inspection and plays an important role in automatic inspection system design. A good approach for pattern definition and extraction will make the following PCB diagnosis easy and efficient. The window-based technique has great potential in PCB patterns extraction due to its simplicity. The conventional window-based pattern extraction methods, such as Small Seeds Window Extraction method (SSWE) and Large Seeds Window Extraction method (LSWE), have the problems of losing some useful copper traces and splitting slanted-lines into too many small similar windows. These methods introduce the difficulty and computation intensive in automatic inspection. In this paper, a novel method called Contour Based Window Extraction (CBWE) algorithm is proposed for improvement. In comparison with both SSWE and LSWE methods, the CBWE algorithm has several advantages in application. Firstly, all traces can be segmented and enclosed by a valid window. Secondly, the type of the entire horizontal or vertical line of copper trace is preserved. Thirdly, the number of the valid windows is less than that extracted by SSWE and LSWE. From the experimental results, the proposed CBWE algorithm is demonstrated to be very effective in basic pattern extraction from bare PCB image analysis.

A simple method for interleaving operation suitable for paralleled converter system is proposed. This method automatically detects the number of converters and adjusts phases between converter modules equally for any number of modules in the system. The method is realized by simple analog circuit which is easily implemented as conventional PWM controller IC. Principle of multiphase controlling circuit is introduced, and the influence of non-ideal circuit parameters on interleaving operation are discussed. A compensator for reducing phase error is also proposed to achieve wide-use application. Experimental and analytical results confirm the effectiveness of the proposed method.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

Low-density parity-check (LDPC) codes are one of the most promising next-generation error-correcting codes. For practical use, efficient methods for encoding of LDPC codes are needed and have to be studied. However, it seems that no general encoding methods suitable for hardware implementation have been proposed so far and for randomly constructed LDPC codes there have been no other methods than the simple one using generator matrices. In this paper we show that some classes of quasi-cyclic LDPC codes based on circulant permutation matrices, specifically LDPC codes based on array codes and a special class of Sridhara-Fuja-Tanner codes and Fossorier codes can be encoded by division circuits as cyclic codes, which are very easy to implement. We also show some properties of these codes.

MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.

This paper introduces τk notation to be used to assess test generation complexity of classes of sequential circuits. Using τk notation, we reconsider and restate the time complexity of test generation for existing classes of acyclic sequential circuits. We also introduce a new DFT method called feedback shift register (FSR) scan design technique, which is extended from the scan design technique. Therefore, for a given sequential circuit, the corresponding FSR scan designed circuit has always equal or lower area overhead and test application time than the corresponding scan designed circuit. Furthermore, we identify some new classes of sequential circuits that contain some cyclic sequential circuits, which are τ-equivalent and τ2-bounded. These classes are the l-length-bounded testable circuits, l-length-bounded validity-identifiable circuits, t-time-bounded testable circuits and t-time-bounded validity-identifiable circuits. In addition, we provide two examples of circuits belonging to these classes, namely counter-cycle finite state machine realizations and state-shiftable finite state machine realizations. Instead of using a DFT method, a given sequential circuit described at the finite state machine (FSM) level can be synthesized using another test methodology called synthesis for testability (SFT) into a circuit that belongs to one of the easily testable classes of cyclic sequential circuits.

This paper presents a frequency-controllable image rejection mixer in heterodyne architecture for 2 GHz applications based on TSMC 0.18 µm CMOS technology. The designed mixer uses a notch filter to suppress the image signal and allows precise tuning the image frequencies. An image rejection of 20-70 dB is obtained in a 200 MHz of bandwidth. The simulation results show single-side band (SSB) NF is improved 3.7 dB, the voltage conversion gain of 14.7 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34 mW.

We have developed new current demultiplexer TFT circuits for AMOLED and applied the circuits to 2.2-in. QVGA AMOLED. The combination of the current demultiplexer and our voltage boosted current programmed pixel can achieve good uniformity of display image and a compact module.